公开(公告)号：US20210342134A1

公开(公告)日：2021-11-04

申请号：US17033751

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Lihu Rappoport ,  Jared W. Stark ,  Jeffrey Baxter ,  Israel Diamand ,  Pavel Fridman ,  Ibrahim Hur ,  Nir Tell

IPC: G06F8/41

Abstract: Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.

公开(公告)号：US20190303294A1

公开(公告)日：2019-10-03

申请号：US15940712

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Wim Heirman ,  Kristof Du Bois ,  Yves Vandriessche ,  Stijn Eyerman ,  Ibrahim Hur ,  Erik Hallnor

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/0871 ,  G06F12/128

Abstract: Embodiment of this disclosure provides a mechanism to store cache lines in dedicated cache of an idle core. In one embodiment, a multi-core processor comprising a first core, a second core, a first cache, a second cache, a third cache, and a cache controller unit is provided. The cache controller is operatively coupled to at least the first cache, the second cache, and the third cache. The cache controller is to evict a first line from the first cache, wherein the first core is in an active state. Responsive to the evicting of the first line, the first line is stored in the third cache. Responsive to storing the first line, a second line is evicted from the third cache. Responsive to evicting the second line, the second line is stored in the second cache when the second core is in an idle state.

公开(公告)号：US10303609B2

公开(公告)日：2019-05-28

申请号：US15718845

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Wim Heirman ,  Kristof Du Bois ,  Yves Vandriessche ,  Stijn Eyerman ,  Ibrahim Hur

IPC: G06F12/0862

Abstract: Embodiments of apparatuses, methods, and systems for independent tuning of multiple hardware prefetchers are described. In an embodiment, an apparatus includes a processor core, a cache memory, a hardware prefetcher, and a prefetch tuner. The hardware prefetcher is to prefetch data for the processor core from a system memory to the cache memory. The prefetch tuner is to adjust a prefetch rate of the hardware prefetcher based on a fraction of late prefetches. The prefetch tuner includes a late prefetch counter to count a number of late prefetches for the hardware prefetcher, a prefetch counter to count a number of prefetches for the hardware prefetcher, and a late prefetch calculator to calculate the fraction of late prefetches based on the number of late prefetches and the number of prefetches.

公开(公告)号：US20190004920A1

公开(公告)日：2019-01-03

申请号：US15638727

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Yves Vandriessche ,  Wim Heirman ,  Ibrahim Hur ,  Kristof du Bois ,  Stijn Eyerman

IPC: G06F11/34 ,  G06F17/50 ,  G06N99/00

Abstract: Technologies for processor architecture simulation with machine learning include a computing device that simulates performance of a processor executing training programs with a simulation model. The computing device captures ground truth performance statistics of the processor executing the training programs, for example using a cycle-accurate simulator. The computing device collects training simulation statistics from the simulation model and trains an error model with the training simulation statistics as feature vector and with the ground truth performance statistics. The computing device may simulate performance of the processor executing a test program, capture test simulation statistic from the simulation model, and predict a predicted error of the simulation model using the error model with the test simulation statistics as feature vector. The computing device may adjust output of the simulation model or adapt execution of the simulation model based on the predicted error. Other embodiments are described and claimed.