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公开(公告)号：US10949945B2
公开(公告)日：2021-03-16
申请号：US16872046
申请日：2020-05-11
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , James A. Valerio , David Puffer , Abhishek R. Appu , Stephen Junkins
IPC: G06T1/60 , G06T1/20 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/0888
Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.
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公开(公告)号：US20200342564A1
公开(公告)日：2020-10-29
申请号：US16872046
申请日：2020-05-11
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , James A. Valerio , David Puffer , Abhishek R. Appu , Stephen Junkins
IPC: G06T1/20 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/0888 , G06T1/60
Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.
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公开(公告)号：US10796667B2
公开(公告)日：2020-10-06
申请号：US16599175
申请日：2019-10-11
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan K. Bhiravabhatla , Arthur D. Hunter, Jr. , Wei-Yu Chen , Subramaniam M. Maiyuran
IPC: G09G5/36 , G06F12/0875 , G06F9/46 , G09G5/00 , G06F12/084 , G06F12/0811
Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.
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公开(公告)号：US10521875B2
公开(公告)日：2019-12-31
申请号：US15477038
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Altug Koker , Balaji Vembu , Joydeep Ray , James A. Valerio , Abhishek R. Appu
Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a processing array including multiple compute blocks, each compute block including multiple processing clusters and a thread dispatch unit to dispatch threads of a workload to the multiple compute blocks based on a parallelism metric, wherein the thread dispatch unit, based on the parallelism metric, is to perform one of a first operation and a second operation, the first operation to distribute threads across the multiple compute blocks and the second operation is to concentrate threads within one of the multiple compute blocks.
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公开(公告)号：US20190340018A1
公开(公告)日：2019-11-07
申请号：US16379565
申请日：2019-04-09
Applicant: Intel Corporation
Inventor： Altug Koker , Joydeep Ray , Balaji Vembu , James A. Valerio , Abhishek R. Appu
Abstract: A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.
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Patent Agency Ranking
公开(公告)号：US20190251652A1
公开(公告)日：2019-08-15
申请号：US16252379
申请日：2019-01-18
Applicant: Intel Corporation
Inventor： Balaji Vernbu , Murali Rarnadoss , Guei-Yuan Lueh , Subramaniam M. Maiyuran , Abhishek R. Appu , Joydeep Ray , Altug Koker , James A. Valerio , Eric J. Hoekstra , Arthur D. Hunter, JR.
Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.
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公开(公告)号：US10235736B2
公开(公告)日：2019-03-19
申请号：US15493420
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , Subramaniam M. Maiyuran , Abhishek R. Appu , Joydeep Ray , Altug Koker , James A. Valerio , Eric J. Hoekstra , Arthur D. Hunter, Jr.
Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.
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公开(公告)号：US20190018799A1
公开(公告)日：2019-01-17
申请号：US16113174
申请日：2018-08-27
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Joydeep Ray , James A. Valerio , Altug Koker , Prasoonkumar P. Surti , Balaji Vembu , Wenyin Fu , Bhushan M. Borole , Kamal Sinha
IPC: G06F12/128 , G06F13/40 , G06F12/0811 , G06T1/20
CPC classification number: G06F12/128 , G06F12/0811 , G06F12/084 , G06F12/0897 , G06F12/12 , G06F13/4022 , G06F2212/1021 , G06F2212/283 , G06F2212/601 , G06F2212/70 , G06T1/60
Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.
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公开(公告)号：US11494232B2
公开(公告)日：2022-11-08
申请号：US17103626
申请日：2020-11-24
Applicant: Intel Corporation
Inventor： Altug Koker , Joydeep Ray , Balaji Vembu , James A. Valerio , Abhishek R. Appu
Abstract: A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.
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公开(公告)号：US11227360B2
公开(公告)日：2022-01-18
申请号：US16714862
申请日：2019-12-16
Applicant: Intel Corporation
Inventor： Altug Koker , Balaji Vembu , Joydeep Ray , James A. Valerio , Abhishek R. Appu
Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a processing array including multiple compute blocks, each compute block including multiple processing clusters and a thread dispatch unit to dispatch threads of a workload to the multiple compute blocks based on a parallelism metric, wherein the thread dispatch unit, based on the parallelism metric, is to perform one of a first operation and a second operation, the first operation to distribute threads across the multiple compute blocks and the second operation is to concentrate threads within one of the multiple compute blocks.
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