公开(公告)号：US09934124B2

公开(公告)日：2018-04-03

申请号：US14732028

申请日：2015-06-05

Applicant: Intel Corporation

Inventor： Furat F. Afram ,  Jeffrey J. Cook ,  Paul Caprioli

IPC: G06F11/36

CPC classification number: G06F11/3624 ,  G06F11/3636

Abstract: In an embodiment, a processor includes execution logic to execute binary translated (BT) code that is translated from native architecture (NA) code. The processor also includes processor trace (PT) logic to output trace information responsive to execution of a BT direct branch instruction in the BT code when the NA code includes an NA direct branch instruction that corresponds to the BT direct branch instruction. The trace information is to include an indication of an NA outcome associated with an execution of the NA direct branch instruction. The trace information is to be based on a BT outcome associated with the execution of the BT direct branch instruction. Other embodiments are described and claimed.