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公开(公告)号：US20160272150A1
公开(公告)日：2016-09-22
申请号：US14660631
申请日：2015-03-17
Applicant: Intel Corporation
Inventor： Kshitij A. Doshi , George J. Chaltas
CPC classification number: B60R22/48 , B60N2/002 , B60N2/26 , B60N2002/2815 , B60R2022/4816 , B60R2022/4858 , G08B21/02 , G08B21/22 , G08B23/00 , G08B25/10
Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with providing alerts to a caregiver in a vehicle. In various embodiments, an apparatus may include a first sensor coupled with a restraint to provide a restraint indicator, a second sensor coupled with a securing component to provide an attachment indicator, and an alert module operated by one or more processors to cause a wireless transmitter to transmit an alert signal based at least in part on the restraint indicator and the attachment indicator. In various embodiments, a warning apparatus may include an output device and a warning module operated by one or more processors to activate the output device based at least in part on a wireless alert signal from a car seat in a vehicle that indicates the car seat is in use.
Abstract translation: 在实施例中，描述与向车辆中的照顾者提供警报相关联的装置，方法和存储介质（暂时性和非暂时性）。 在各种实施例中，装置可以包括与限制器耦合以提供约束指示器的第一传感器，与固定部件耦合以提供附接指示器的第二传感器以及由一个或多个处理器操作以使无线发射器 至少部分地基于约束指示符和附件指示符来发送警报信号。 在各种实施例中，警报装置可以包括输出装置和由一个或多个处理器操作的警告模块，以至少部分地基于来自车辆中的汽车座椅的无线警报信号来激活输出装置，其指示汽车座椅是 正在使用。
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22.发明授权公开(公告)号：US09389976B2
公开(公告)日：2016-07-12
申请号：US14248913
申请日：2014-04-09
Applicant: Intel Corporation
Inventor： Kshitij A. Doshi , Rahul Khanna , Minh T. Le
CPC classification number: G06F17/30578 , G06F3/0619 , G06F3/0644 , G06F3/065 , G06F3/067 , G06F11/1482 , G06F11/203 , G06F11/2048 , G06F11/2097 , G06F17/30368 , G06F2201/84 , G06F2201/855 , G06F2201/87
Abstract: Technologies for distributed durable data replication include a computing device having persistent memory that stores a memory state and an update log. The computing device isolates a host partition from a closure partition. The computing device may sequester one or more processor cores for use by the closure partition. The host partition writes transaction records to the update log prior to writing state changes to persistent memory. A replication service asynchronously transmits log records to a remote computing device, which establishes a replica update log in persistent memory. If the host partition fails, the closure partition transmits remaining log records from the update log to the remote computing device. The update log may be quickly replayed when recovering the computing device from failure. The remote computing device may also replay the replica update log to update a remote copy of the state data. Other embodiments are described and claimed.
Abstract translation: 用于分布式持久数据复制的技术包括具有存储存储器状态和更新日志的持久存储器的计算设备。 计算设备将主机分区与封闭分区隔离开来。 计算设备可以隔离一个或多个处理器核以供封闭分区使用。 在将状态更改写入持久内存之前，主机分区将事务记录写入更新日志。 复制服务将日志记录异步发送到远程计算设备，远程计算设备在持久存储器中建立副本更新日志。 如果主机分区失败，则关闭分区将剩余的日志记录从更新日志传输到远程计算设备。 从故障恢复计算设备时，可能会快速重播更新日志。 远程计算设备还可以重放副本更新日志以更新状态数据的远程副本。 描述和要求保护其他实施例。
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公开(公告)号：US12038861B2
公开(公告)日：2024-07-16
申请号：US17973268
申请日：2022-10-25
Applicant: Intel Corporation
Inventor： Francesc Guim Bernat , Da-Ming Chiang , Kshitij A. Doshi , Suraj Prabhakaran , Mark A. Schmisseur
IPC: G06F13/40 , G06F9/455 , G06F9/50 , G06F9/54 , G06F13/362 , G06F13/42 , G06N3/02 , G06N3/04 , G06N3/045 , G06N3/08
CPC classification number: G06F13/4068 , G06F9/45533 , G06F9/5027 , G06F9/54 , G06F13/362 , G06F13/4265 , G06F13/4282 , G06N3/02 , G06N3/04 , G06N3/045 , G06N3/08 , G06F2213/0026
Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.
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公开(公告)号：US11586575B2
公开(公告)日：2023-02-21
申请号：US17584092
申请日：2022-01-25
Applicant: Intel Corporation
Inventor： Francesc Guim Bernat , Da-Ming Chiang , Kshitij A. Doshi , Suraj Prabhakaran , Mark A. Schmisseur
IPC: G06F13/40 , G06F13/362 , G06N3/04 , G06F13/42 , G06F9/455 , G06N3/08 , G06F9/50 , G06F9/54 , G06N3/02
Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.
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公开(公告)号：US11568022B2
公开(公告)日：2023-01-31
申请号：US17156119
申请日：2021-01-22
Applicant: Intel Corporation
Inventor： Dmitry Y. Babokin , Kshitij A. Doshi , Vadim Sukhomlinov
Abstract: Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.
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Patent Agency Ranking
公开(公告)号：US11500681B2
公开(公告)日：2022-11-15
申请号：US15637003
申请日：2017-06-29
Applicant: Intel Corporation
Inventor： Francesc Guim Bernat , Kshitij A. Doshi , Andrew J. Herdrich , Edwin Verplanke , Daniel Rivas Barragan
IPC: G06F9/50 , H04L67/1008 , G06F13/38 , G06F9/46
Abstract: A compute device includes one or more processors, one or more resources capable of being utilized by the one or more processors, and a platform interconnect to facilitate communication of messages between the one or more processors and the one or more resources. The compute device is to obtain class of service data for one or more workloads to be executed by the compute device. The class of service data is indicative of a capacity of one or more of the resources to be utilized in the execution of each corresponding workload. The compute device is also to execute the one or more workloads and manage the amount of traffic transmitted through the platform interconnect for each corresponding workload as a function of the class of service data as the one or more workloads are executed.
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公开(公告)号：US20220324441A1
公开(公告)日：2022-10-13
申请号：US17741124
申请日：2022-05-10
Applicant: Intel Corporation
Inventor： David Gomez Gutierrez , Javier Felip Leon , Kshitij A. Doshi , Leobardo E. Campos Macias , Nilesh Amar Ahuja , Omesh Tickoo
IPC: B60W30/095 , B60W50/14 , G06V20/58 , G06V40/10
Abstract: An apparatus comprising a memory to store an observed trajectory of a pedestrian, the observed trajectory comprising a plurality of observed locations of the pedestrian over a first plurality of timesteps; and a processor to generate a predicted trajectory of the pedestrian, the predicted trajectory comprising a plurality of predicted locations of the pedestrian over the first plurality of timesteps and over a second plurality of timesteps occurring after the first plurality of timesteps; determine a likelihood of the predicted trajectory based on a comparison of the plurality of predicted locations of the pedestrian over the first plurality of timesteps and the plurality of observed locations of the pedestrian over the first plurality of timesteps; and responsive to the determined likelihood of the predicted trajectory, provide information associated with the predicted trajectory to a vehicle to warn the vehicle of a potential collision with the pedestrian.
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公开(公告)号：US11468329B2
公开(公告)日：2022-10-11
申请号：US17025643
申请日：2020-09-18
Applicant: Intel Corporation
Inventor： Francesc Guim Bernat , Suraj Prabhakaran , Kshitij A. Doshi , Da-Ming Chiang
Abstract: Examples include techniques to manage training or trained models for deep learning applications. Examples include routing commands to configure a training model to be implemented by a training module or configure a trained model to be implemented by an inference module. The commands routed via out-of-band (OOB) link while training data for the training models or input data for the trained models are routed via inband links.
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公开(公告)号：US11467888B2
公开(公告)日：2022-10-11
申请号：US17111581
申请日：2020-12-04
Applicant: Intel Corporation
Inventor： Vadim Sukhomlinov , Kshitij A. Doshi
Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.
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公开(公告)号：US11216306B2
公开(公告)日：2022-01-04
申请号：US15636969
申请日：2017-06-29
Applicant: Intel Corporation
Inventor： Francesc Guim Bernat , Kshitij A. Doshi , Daniel Rivas Barragan , Alejandro Duran Gonzalez , Harald Servat
IPC: H04L29/08 , G06F9/50 , H04W8/22 , H04L29/12 , H04L12/741
Abstract: Technologies for dynamically sharing remote resources include a computing node that sends a resource request for remote resources to a remote computing node in response to a determination that additional resources are required by the computing node. The computing node configures a mapping of a local address space of the computing node to the remote resources of the remote computing node in response to sending the resource request. In response to generating an access to the local address, the computing node identifies the remote computing node based on the local address with the mapping of the local address space to the remote resources of the remote computing node and performs a resource access operation with the remote computing node over a network fabric. The remote computing node may be identified with system address decoders of a caching agent and a host fabric interface. Other embodiments are described and claimed.
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