公开(公告)号：US12002745B2

公开(公告)日：2024-06-04

申请号：US17544693

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew J. Manusharow ,  Krishna Bharath ,  William J. Lambert ,  Robert L. Sankman ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Feras Eid ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Suddhasattwa Nad ,  Telesphor Kamgaing

IPC: H05K1/02 ,  H01F17/00 ,  H01F17/06 ,  H01F27/28 ,  H01F27/40 ,  H01F41/04 ,  H01G4/18 ,  H01G4/252 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L23/49838 ,  H01F17/0006 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/041 ,  H01G4/33 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/66 ,  H01L28/00 ,  H01L28/10 ,  H01L28/60 ,  H01F2027/2809 ,  H01L2223/6661

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US11227825B2

公开(公告)日：2022-01-18

申请号：US15773030

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew J. Manusharow ,  Krishna Bharath ,  William J. Lambert ,  Robert L. Sankman ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Feras Eid ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Suddhasattwa Nad ,  Telesphor Kamgaing

IPC: H05K1/03 ,  H05K1/16 ,  H01F17/00 ,  H01F17/06 ,  H01L21/02 ,  H01L21/50 ,  H01L21/60 ,  H01L23/48 ,  H01L23/60 ,  G11B5/17 ,  G11B5/31 ,  G11B5/147 ,  G11B5/187 ,  H01L23/498 ,  H01F27/40 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01G4/33 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US10886228B2

公开(公告)日：2021-01-05

申请号：US15774091

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Mathew J. Manusharow ,  Jonathan Rosenfeld

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

公开(公告)号：US20190304911A1

公开(公告)日：2019-10-03

申请号：US15937411

申请日：2018-03-27

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Debendra Mallik ,  Mathew J. Manusharow ,  Jianyong Xie

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48

Abstract: An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.

公开(公告)号：US20190027405A1

公开(公告)日：2019-01-24

申请号：US16141181

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Harold Ryan Chase ,  Mihir K. Roy ,  Mathew J. Manusharow ,  Mark Hlad

IPC: H01L21/768 ,  H05K1/02 ,  H01L23/00 ,  H01L23/48 ,  H01L21/288 ,  H05K3/46 ,  H01L23/552 ,  H01L23/498 ,  H01L23/36

Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.

公开(公告)号：US20170188460A1

公开(公告)日：2017-06-29

申请号：US15461406

申请日：2017-03-16

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/18 ,  H05K3/20 ,  H05K1/18 ,  H05K3/10

CPC classification number: H05K1/116 ,  H05K1/141 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/107 ,  H05K3/182 ,  H05K3/207 ,  H05K3/422 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49128

Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.

公开(公告)号：US09521751B2

公开(公告)日：2016-12-13

申请号：US14085613

申请日：2013-11-20

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H01B7/00 ,  H01B3/50 ,  H05K1/16 ,  H01B7/08 ,  H01B3/48 ,  H01F17/00 ,  H05K1/03 ,  H05K3/10 ,  H05K3/40 ,  H01B3/04 ,  H01B7/02 ,  H05K1/02 ,  H05K3/04 ,  H05K3/26

CPC classification number: H05K3/10 ,  H01B3/485 ,  H01B3/50 ,  H01B7/083 ,  H01F17/0006 ,  H05K1/0222 ,  H05K1/038 ,  H05K1/165 ,  H05K3/043 ,  H05K3/103 ,  H05K3/22 ,  H05K3/26 ,  H05K3/30 ,  H05K3/40 ,  H05K3/4046 ,  H05K2201/029 ,  H05K2201/097 ,  H05K2201/09809 ,  H05K2201/10287 ,  H05K2201/1081 ,  H05K2203/0228 ,  H05K2203/025 ,  H05K2203/1461 ,  H05K2203/175 ,  H05K2203/30

Abstract: A substrate package includes a woven fabric having electrically non-conductive strands woven between electrically conductive strands including wire strands, co-axial strands, and/or an inductor pattern of strands. The package may be formed by an inexpensive and high throughput process that first weaves the non-conductive strands (e.g., glass) between the conductive strands to form a circuit board pattern of conductive strands in a woven fabric. Next, the woven fabric is impregnated with a resin material to form an impregnated fabric, which is then cured to form a cured fabric. The upper and lower surfaces of the cured fabric are subsequently planarized. Planarizing segments and exposes ends of the wire, co-axial, and inductor pattern strands. Since the conductive strands were formed integrally within the planarized woven fabric, the substrate has a high mechanical stability and provides conductor strand based electrical components built in situ in the substrate package.

Abstract translation: 衬底封装包括织造织物，其具有在导电股线之间编织的非导电股线，包括线股，同轴股线和/或股线的电感器图案。 封装可以通过廉价且高通量的工艺来形成，该工艺首先在导电股线之间编织非导电股线（例如玻璃），以形成机织织物中导电股线的电路板图案。 接下来，用树脂材料浸渍织物以形成浸渍织物，然后将其固化以形成固化织物。 随后将固化的织物的上表面和下表面平坦化。 平面化节段并露出导线，同轴和电感图案线的端部。 由于导电丝线整体地形成在平面织造织物内，所以基底具有高的机械稳定性，并提供了在基底包装中原位构建的基于导线的电气部件。

公开(公告)号：US20160204049A1

公开(公告)日：2016-07-14

申请号：US15046280

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L23/482 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

公开(公告)号：US08772924B2

公开(公告)日：2014-07-08

申请号：US13852277

申请日：2013-03-28

Applicant: Intel Corporation

Inventor： Ravi Nalla ,  Mathew J. Manusharow

IPC: H01L21/02

CPC classification number: H01L24/20 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/13021 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24227 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H05K1/0209 ,  H05K1/185 ,  H05K3/4682

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，形成围绕管芯的电介质材料，在电介质材料中形成堆积层，以形成无芯无阻堆积的封装结构，以及图案化载体材料以在封装结构上形成微通道结构。

公开(公告)号：US10784204B2

公开(公告)日：2020-09-22

申请号：US16305012

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Richard J. Dischler ,  Jeff C. Morriss ,  Zhiguo Qian ,  Wilfred Gomes ,  Yu Amos Zhang ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Sriram Srinivasan ,  Yidnekachew S. Mekonnen ,  Sanka Ganesan ,  Eduard Roytman ,  Mathew J. Manusharow

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/528 ,  H01L23/60 ,  H01L23/00 ,  H01L25/065

Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.