公开(公告)号：US20230268410A1

公开(公告)日：2023-08-24

申请号：US17677909

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Wilfred Gomes ,  Sagar Suthram

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/66 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/04 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78696

Abstract: IC devices including vertical TFETs are disclosed. An example IC device includes a substrate, a channel region, a first region, and a second region. One of the first and second regions is a source region and another one is a drain region. The first region includes a first semiconductor material. The second region includes a second semiconductor material that may be different from the first semiconductor material. The first region and the second region are doped with opposite types of dopants. The channel region includes a third semiconductor material that may be different from the first or second semiconductor material. The channel region is between the first region and the second region. The first region is between the channel region and the substrate. In some embodiments, the first or second region is formed through layer transfer or epitaxy (e.g., graphoepitaxy, chemical epitaxy, or a combination of both).

公开(公告)号：US20230268392A1

公开(公告)日：2023-08-24

申请号：US17678928

申请日：2022-02-23

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Sagar Suthram ,  Tahir Ghani ,  Anand S. Murthy

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/0669 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/78618 ,  H01L29/66742 ,  H01L27/0886

Abstract: The scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. As transistors of the ICs become smaller, their gate lengths become smaller, leading to undesirable short-channel effects such as poor leakage, poor subthreshold swing, drain-induced barrier lowering, etc. Embodiments of the present disclosure are based on recognition that extending at least one of two S/D contacts of a transistor into a channel layer while keeping it separated from a corresponding gate stack by a channel material may allow keeping the footprint of the transistor relatively small while effectively increasing transistor's effective gate length and thus reducing the negative impacts of short-channel effects. This architecture may be optimized even further if transistors are to be operated at relatively low temperatures, e.g., below 200 Kelvin degrees or lower. For multiple transistors, some of the S/D contacts may be shared to further increase transistor density.

公开(公告)号：US20250062278A1

公开(公告)日：2025-02-20

申请号：US18452152

申请日：2023-08-18

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Ravindranath Vithal Mahajan ,  Abhishek A. Sharma ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta ,  Michael Crocker ,  Aaron Gorius

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.

公开(公告)号：US20240222347A1

公开(公告)日：2024-07-04

申请号：US18148338

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Kuljit S. Bains ,  Wilfred Gomes ,  Don Douglas Josephson ,  Surhud V. Khare ,  Christopher Philip Mozak ,  Randy B. Osborne ,  Pushkar Ranade ,  Abhishek Anil Sharma

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L24/16 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: In embodiments herein, an integrated circuit device includes a logic die with processor circuitry and a memory die coupled to the logic die. The memory die includes a first memory module comprising a first memory bank and first control circuitry, a second memory module comprising a second memory bank and second control circuitry, and a scribe line on a surface of the memory die between the first memory module and the second memory module. The first memory module is not electrically connected to the second memory module, and each memory module include through silicon vias (TSVs) to electrically connect a top side of the memory module and a bottom side of the memory module (e.g., for three-dimensional stacking in the integrated circuit device).

公开(公告)号：US20240222321A1

公开(公告)日：2024-07-04

申请号：US18148533

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L2225/06548

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The second IC die is between the first IC die and the package substrate. The first IC die includes: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US12013442B2

公开(公告)日：2024-06-18

申请号：US16147564

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Enlan Yuan ,  David Sanchez ,  Amit Paliwal ,  Manish Sharma ,  Sairam Subramanian ,  Sagar Suthram

IPC: H01L21/66 ,  G01R31/28 ,  G01R31/307 ,  G01R31/50 ,  H01L27/02

CPC classification number: G01R31/50 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/307 ,  H01L22/32 ,  H01L22/34

Abstract: Embodiments of the present disclosure relate to in-line detection of electrical fails on integrated circuits. One embodiment is an apparatus including a device region with integrated circuits and a test region for in-line failure detection of the integrated circuits using an in-line voltage contrast test, the apparatus comprising: a substrate including a first area for the device region and a second different area for the test region; metal layers formed over both areas; wherein the integrated circuits are formed from first sections of the layers; and wherein a second section of an upper metal layer of the layers is segmented into test segments, each test segment to exhibit a predefined response during the in-line voltage contrast test depending on whether the test segment is shorted, or not, to the substrate and/or the second section of a gate layer of the layer. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20240107749A1

公开(公告)日：2024-03-28

申请号：US17935639

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy ,  Sagar Suthram

IPC: H01L27/108 ,  G11C5/02 ,  G11C11/404

CPC classification number: H01L27/10829 ,  G11C5/025 ,  G11C11/4045

Abstract: Various arrangements for IC devices implementing memory with one access transistor for multiple capacitors are disclosed. An example IC device includes a memory array of M memory units, where each memory unit includes an access transistor and N capacitors coupled to the access transistor. A portion of the capacitors are formed in one or more layers above the access transistor, and a portion of the capacitors are formed in one or more layers below the access transistor. The capacitors in a particular memory unit may be coupled to a single via or to individual vias. In some embodiments, some of the vias are backside vias.

公开(公告)号：US20240105811A1

公开(公告)日：2024-03-28

申请号：US17955209

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Sagar Suthram ,  Tahir Ghani ,  Anand Murthy ,  Wilfred Gomes ,  Pushkar Ranade

IPC: H01L29/51 ,  H01L21/28 ,  H01L27/11507 ,  H01L27/1159

CPC classification number: H01L29/516 ,  H01L27/11507 ,  H01L27/1159 ,  H01L29/40111 ,  G11C11/221

Abstract: An integrated circuit (IC) die includes a plurality of ferroelectric tunnel junction (FTJ) devices, where at least one FTJ of the plurality of FTJ devices comprises first electrode, a second electrode, ferroelectric material disposed between the first and second electrodes, and interface material disposed between at least one of the first and second electrodes and the ferroelectric material. Other embodiments are disclosed and claimed.

公开(公告)号：US20240105585A1

公开(公告)日：2024-03-28

申请号：US17955245

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Pushkar Ranade ,  Tahir Ghani ,  Wilfred Gomes ,  Sagar Suthram ,  Anand Murthy

IPC: H01L23/522 ,  H01L23/427

CPC classification number: H01L23/5223 ,  H01L23/427

Abstract: An embodiment of a capacitor in the back-side layers of an IC die may comprise any type of solid-state electrolyte material disposed between electrodes of the capacitor. Another embodiment of a capacitor anywhere in an IC die may include one or more materials selected from the group of indium oxide, indium nitride, gallium oxide, gallium nitride, zinc oxide, zinc nitride, tungsten oxide, tungsten nitride, tin oxide, tin nitride, nickel oxide, nickel nitride, niobium oxide, niobium nitride, cobalt oxide, and cobalt nitride between electrodes of the capacitor. Other embodiments are disclosed and claimed.

公开(公告)号：US20240008244A1

公开(公告)日：2024-01-04

申请号：US17856879

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Sagar Suthram ,  Wilfred Gomes ,  Anand Murthy ,  Tahir Ghani

IPC: H01L27/108

CPC classification number: H01L27/108

Abstract: Bits are stored in cells having two transistors between two parallel bitlines. In a memory array, first and second transistor channels in a bit cell are parallel and offset and coupled to first and second bitlines, respectively, which are also parallel and offset. Adjacent bit cells share corresponding transistor channel structures. The transistor channels may be orthogonal to the bitlines. The memory array may be on an integrated circuit (IC) die, which may be coupled to a power supply in an IC system. In an IC system, the memory array may be coupled to a power supply and a cooling structure.