公开(公告)号：US09996466B2

公开(公告)日：2018-06-12

申请号：US15488324

申请日：2017-04-14

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika ,  Rowel S. Garcia

IPC: G06F12/08 ,  G06F12/0802 ,  G06F12/0871

CPC classification number: G06F12/0802 ,  G06F12/0871 ,  G06F12/0886 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/222 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.

公开(公告)号：US09823731B2

公开(公告)日：2017-11-21

申请号：US14724943

申请日：2015-05-29

Applicant: Intel Corporation

Inventor： Nathaniel G. Burke ,  Sanjeev N. Trika

IPC: G06F12/00 ,  G06F1/32 ,  G06F12/02 ,  G06F3/06 ,  G11C7/10 ,  G06F12/06

CPC classification number: G06F1/3287 ,  G06F1/32 ,  G06F1/3212 ,  G06F1/3225 ,  G06F1/3268 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/0634 ,  G06F3/0688 ,  G06F12/02 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0638 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C7/1072 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154

Abstract: An apparatus includes a storage resource to store data. The data can be accessible by a host computer system. The apparatus includes a set of dynamically powered volatile memory devices that are configured to store mapping information. The mapping information maps logical addresses of received access requests to corresponding physical addresses of the storage resource to which the access requests pertain. In accordance with received mode setting information, the controller logic adaptively controls power settings of the volatile memory devices storing the mapping information. If an abundance of power such as 120 VAC power is available, more of volatile memory devices can be powered to store a greater portion of the mapping information. If only battery power is available, fewer than all of the volatile memory devices can be powered to store a smaller portion of the mapping information.

公开(公告)号：US09652384B2

公开(公告)日：2017-05-16

申请号：US14572689

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika ,  Rowel S. Garcia

IPC: G06F12/08 ,  G06F12/0802 ,  G06F12/0871

CPC classification number: G06F12/0802 ,  G06F12/0871 ,  G06F12/0886 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/222 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.

公开(公告)号：US20170060436A1

公开(公告)日：2017-03-02

申请号：US14843581

申请日：2015-09-02

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika ,  Knut S. Grimsrud ,  Piotr Wysocki

IPC: G06F3/06 ,  G06F11/20

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F11/2015 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0888 ,  G06F2201/805 ,  G06F2212/7203 ,  Y02D10/13

Abstract: Technologies for establishing and managing a high-performance memory region of a solid state drive include reserving a region of a volatile memory of the solid state drive for storage of host data. Memory accesses received from a host may be directed toward the reserved region of the volatile memory or toward a non-volatile memory of the solid state drive. Due to the structure of the volatile memory, memory accesses to the reserved region may exhibit lower access timing relative to memory accesses to the non-volatile memory. As such, the reserved region may be utilized as storage space for journaling and logging of data and/or other applications. Upon shutdown or a power failure event, data stored in the reserved region of the volatile memory is copied to the non-volatile memory and subsequently reinstated to the volatile memory upon the next initialization event.

Abstract translation: 用于建立和管理固态驱动器的高性能存储器区域的技术包括保留用于存储主机数据的固态驱动器的易失性存储器的区域。 从主机接收到的存储器访问可以指向易失性存储器的保留区域或朝向固态驱动器的非易失性存储器。 由于易失性存储器的结构，相对于对非易失性存储器的存储器访问，对保留区域的存储器访问可以呈现较低的访问时序。 因此，保留区域可以用作用于日志记录和记录数据和/或其他应用的存储空间。 在关闭或电源故障事件时，存储在易失性存储器的保留区域中的数据被复制到非易失性存储器中，并且随后在下一个初始化事件时恢复到易失性存储器。

公开(公告)号：US09501402B2

公开(公告)日：2016-11-22

申请号：US14184256

申请日：2014-02-19

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika

IPC: G06F12/08 ,  G06F12/02 ,  G06F11/14

CPC classification number: G06F12/0871 ,  G06F11/1441 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0866 ,  G06F12/0868 ,  G06F2212/1032 ,  G06F2212/222 ,  G06F2212/601

Abstract: A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required.

Abstract translation: 一种方法和系统，用于将永久存储设备中的数据的电力故障安全写回或直写缓存缓存到高速缓存设备的一个或多个高速缓存行。 当存储设备中的数据被缓存时，没有与任何高速缓存行相关联的元数据被原子地写入高速缓存设备。 因此，不需要专门的高速缓存硬件来在数据缓存期间允许元数据的原子写入。

公开(公告)号：US11334253B2

公开(公告)日：2022-05-17

申请号：US16213642

申请日：2018-12-07

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a storage system management unit to manage a storage system having physical storage resources divided into different reliability zones. A data item to be stored in the storage system is to be assigned a particular reliability level by the management unit and is to be stored by the management unit in one of the reliability zones that is to provide a level of protection against data loss that is at least as protective as the particular reliability level.

公开(公告)号：US11054993B2

公开(公告)日：2021-07-06

申请号：US16424329

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Knut S. Grimsrud ,  Sanjeev N. Trika

IPC: G06F3/06 ,  G06F12/0862 ,  G06F12/0868 ,  G06F12/0891

Abstract: An apparatus is described. The apparatus includes peer-to-peer intelligence to be integrated into a mass storage system having a cache and a backing store. The peer-to-peer intelligence is to move data between the cache and backing store without the data passing through main memory.

公开(公告)号：US10606488B2

公开(公告)日：2020-03-31

申请号：US15640169

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Sanjeev N. Trika

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/121 ,  G06F12/02

Abstract: In one embodiment, a storage drive is configured to receive a selective flush command which causes the storage drive to selectively flush write data which has been identified in connection with the selective flush command, from volatile buffer memory to a nonvolatile storage memory. Conversely, write data stored in the volatile buffer memory which is not identified in connection with the selective flush command, may remain unaffected by the selective flush command, and thus may remain stored in the volatile buffer memory without being flushed to the nonvolatile storage memory as a result of the selective flush command. Other aspects are described herein.

公开(公告)号：US10417218B2

公开(公告)日：2019-09-17

申请号：US14757602

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Kshitij A. Doshi ,  Sanjeev N. Trika ,  Sridharan Sakthivelu

IPC: G06F16/23 ,  G06F9/46

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receiving a sequence of transactions, each transaction including a request to write data to a memory device, processing the sequence of transactions, and communicating a response to a host after the sequence of transaction have been completed.

公开(公告)号：US10108339B2

公开(公告)日：2018-10-23

申请号：US14573517

申请日：2014-12-17

Applicant: INTEL CORPORATION

Inventor： Gavin F. Paes ,  Sanjeev N. Trika

IPC: G06F3/06

Abstract: An operating system of a computational device manages access of a plurality of applications to a solid state drive. Separate bands are maintained in the solid state drive for storing writes of at least two different applications of the plurality of applications. Additionally, in other embodiments, a virtual machine manager of a computational device manages access of a plurality of virtual machines to a solid state drive. Separate bands are maintained in the solid state drive for storing writes of at least two different virtual machines of the plurality of virtual machines.