公开(公告)号：US11043627B2

公开(公告)日：2021-06-22

申请号：US16304964

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Paul B. Fischer

IPC: H01L41/083 ,  H01L27/20 ,  H01L29/15 ,  H01L29/20 ,  H03H9/17

Abstract: Techniques are disclosed for co-integrating thin-film bulk acoustic resonator (TFBAR, also called FBAR) devices and III-N semiconductor transistor devices. In accordance with some embodiments, a given TFBAR device may include a superlattice structure comprising alternating layers of an epitaxial piezoelectric material, such as aluminum nitride (AlN), and any one, or combination, of other III-N semiconductor materials. For instance, aluminum indium nitride (AlxIn1-xN), aluminum gallium nitride (AlxGa1-xN), or aluminum indium gallium nitride (AlxInyGa1-x-yN) may be interleaved with the AlN, and the particular compositional ratios thereof may be adjusted to customize resonator performance. In accordance with some embodiments, the superlattice layers may be formed via an epitaxial deposition process, allowing for precise control over film thicknesses, in some cases in the range of a few nanometers. In accordance with some embodiments, one or more such TFBAR devices may be formed alongside III-N semiconductor transistor device(s), over a commonly shared semiconductor substrate.

公开(公告)号：US10998260B2

公开(公告)日：2021-05-04

申请号：US16462889

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Sanaz K. Gardner

IPC: H01L23/522 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L29/06 ,  H01L23/532

Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.

公开(公告)号：US20200373421A1

公开(公告)日：2020-11-26

申请号：US16419179

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/778 ,  H01L29/20 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor arrangements that may reduce nonlinearity of off-state capacitance of the III-N transistors. In various aspects, III-N transistor arrangements limit the extent of access regions of the transistors, compared to conventional implementations, which may limit the depletion of the access regions. Due to the limited extent of the depletion regions of a transistor, the off-state capacitance may exhibit less variability in values across different gate-source voltages and, hence, exhibit a more linear behavior during operation.

公开(公告)号：US20200295172A1

公开(公告)日：2020-09-17

申请号：US16297837

申请日：2019-03-11

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Paul B. Fischer ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/08 ,  H01L29/04 ,  H01L29/66

Abstract: Disclosed herein are IC structures, packages, and device assemblies with III-N transistors that include additional materials, referred to herein as “stressor materials,” which may be selectively provided over portions of polarization materials to locally increase or decrease the strain in the polarization material. Providing a compressive stressor material may decrease the tensile stress imposed by the polarization material on the underlying portion of the III-N semiconductor material, thereby decreasing the two-dimensional electron gas (2DEG) and increasing a threshold voltage of a transistor. On the other hand, providing a tensile stressor material may increase the tensile stress imposed by the polarization material, thereby increasing the 2DEG and decreasing the threshold voltage. Providing suitable stressor materials enables easier and more accurate control of threshold voltage compared to only relying on polarization material recess.

公开(公告)号：US20200279932A1

公开(公告)日：2020-09-03

申请号：US16289824

申请日：2019-03-01

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Johann Christian Rode ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778 ,  H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L21/28 ,  H01L29/66

Abstract: Disclosed herein are IC structures, packages, and devices that include planar III-N transistors with wrap-around gates and/or one or more wrap-around source/drain (S/D) contacts. An example IC structure includes a support structure (e.g., a substrate) and a planar III-N transistor. The transistor includes a channel stack of a III-N semiconductor material and a polarization material, provided over the support structure, a pair of S/D regions provided in the channel stack, and a gate stack of a gate dielectric material and a gate electrode material provided over a portion of the channel stack between the S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack.

公开(公告)号：US20200266190A1

公开(公告)日：2020-08-20

申请号：US16279102

申请日：2019-02-19

Applicant: INTEL CORPORATION

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L27/06 ,  H01L29/15 ,  H01L29/20 ,  H01L29/778 ,  H01L23/66 ,  H01L23/535 ,  H01L29/66 ,  H01L21/8252

Abstract: An integrated circuit die has a layer of first semiconductor material comprising a Group III element and nitrogen and having a first bandgap. A first transistor structure on a first region of the die has: a quantum well (QW) structure that includes at least a portion of the first semiconductor material and a second semiconductor material having a second bandgap smaller than the first bandgap, a first source and a first drain in contact with the QW structure, and a gate structure in contact with the QW structure between the first source and the first drain. A second transistor structure on a second region of the die has a second source and a second drain in contact with a semiconductor body, and a second gate structure in contact with the semiconductor body between the second source and the second drain. The semiconductor body comprises a Group III element and nitrogen.

公开(公告)号：US10727339B2

公开(公告)日：2020-07-28

申请号：US15119674

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Gilbert Dewey ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Han Wui Then ,  Niloy Mukherjee ,  Sansaptak Dasgupta

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/336 ,  H01L29/66 ,  H01L29/08 ,  H01L29/739

Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

公开(公告)号：US20200227469A1

公开(公告)日：2020-07-16

申请号：US16249493

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Zdravko Boos ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Paul B. Fischer

IPC: H01L27/20 ,  H01L29/20 ,  H01L29/78 ,  H01L41/18 ,  H01L25/18 ,  H03F3/195 ,  H03B5/36

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same substrate or die as resonators of RF filters. An example IC structure includes a support structure (e.g., a substrate), a resonator, provided over a first portion of the support structure, and an III-N transistor, provided over a second portion of the support structure. The IC structure includes a piezoelectric material so that first and second electrodes of the resonator enclose a first portion of the piezoelectric material, while a second portion of the piezoelectric material is enclosed between the channel material of the III-N transistor and the support structure. In this manner, one or more resonators of an RF filter may be monolithically integrated with one or more III-N transistors. Such integration may reduce costs and improve performance by reducing RF losses incurred when power is routed off chip.

公开(公告)号：US20200219878A1

公开(公告)日：2020-07-09

申请号：US16243523

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/423 ,  H01L29/786 ,  H01L23/34 ,  H01L29/66 ,  H01L21/8252

Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a TFT provided over a second portion of the III-N material. Because the III-N transistor and the TFT are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the TFT are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration. Integrating TFTs with III-N transistors may reduce costs and improve performance, e.g., by reducing losses incurred when power is routed off chip in a multi-chip package.

公开(公告)号：US10600787B2

公开(公告)日：2020-03-24

申请号：US16078675

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Peter G. Tolchinsky ,  Roza Kotlyar ,  Valluri R. Rao

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8258 ,  H01L23/498 ,  H01L23/544 ,  H01L29/16 ,  H01L29/205 ,  H01L29/423 ,  H01L29/04 ,  H01L29/417 ,  H01L21/8238 ,  H04B1/38

Abstract: This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate.