公开(公告)号：US20200257827A1

公开(公告)日：2020-08-13

申请号：US16862022

申请日：2020-04-29

Applicant: Intel Corporation

Inventor： Michael E. Kounavis ,  Santosh Ghosh ,  Sergej Deutsch ,  Michael LeMay ,  David M. Durham

IPC: G06F21/64 ,  H04L9/32 ,  G06F21/60 ,  G06F3/06

Abstract: Technologies disclosed herein provide cryptographic computing with memory write access in the core. An example method comprises executing a first instruction of a software entity. The first instruction comprises a first operand comprising a certificate for a memory region in memory. Executing the first instruction includes computing encrypted first data based, at least in part, on a cryptographic algorithm and a first data parameter, determining whether the certificate authorizes the software entity to access the memory region of the memory, and based on determining the certificate in the first operand authorizes the software entity to access the memory region, performing a write operation to store the encrypted first data in the memory region. More specific embodiments include performing the write operation without performing a preceding read operation on the memory region, which may be called a write for ownership.

公开(公告)号：US20190319799A1

公开(公告)日：2019-10-17

申请号：US16455921

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08 ,  G06F9/38

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

公开(公告)号：US20190007219A1

公开(公告)日：2019-01-03

申请号：US15637737

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj R. Sastry

IPC: H04L9/32 ,  H04L9/30

Abstract: Technologies for elliptic curve cryptography (ECC) include a computing device having an ECC engine that reads one or more parameters from a data port. The ECC engine performs operations using the parameters, such as an Elliptic Curve Digital Signature Algorithm (ECDSA). The ECDSA may be performed in a protected mode, in which the ECC engine will ignore inputs. The ECC engine may perform the ECDSA in a fixed amount of time in order to protect against timing side-channel attacks. The ECC engine may perform the ECDSA by consuming a uniform amount of power in order to protect against power side-channel attacks. The ECC engine may perform the ECDSA by emitting a uniform amount of electromagnetic radiation in order to protect against EM side-channel attacks. The ECC engine may perform the ECDSA verify with 384-bit output in order to protect against fault injection attacks.

公开(公告)号：US09967098B2

公开(公告)日：2018-05-08

申请号：US14757658

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj R Sastry

IPC: H04L29/00 ,  H04L9/30 ,  H04L9/14

CPC classification number: H04L9/3066 ,  G06F7/725 ,  G09C1/00 ,  H04L9/14 ,  H04L2209/12 ,  H04L2209/24

Abstract: Embodiments of a system for, and method for using, an elliptic curve cryptography integrated circuit are generally described herein. An elliptic curve cryptography (ECC) operation request may be received. One of a plurality of circuit portions may be instructed to perform the ECC operation. The plurality of circuit portions that may be used include a finite field arithmetic circuit portion, an EC point addition and doubler circuit portion, a finite field exponentiation circuit portion, and a point multiplier circuit portion. The result of the ECC operation may then be output.

公开(公告)号：US20170180131A1

公开(公告)日：2017-06-22

申请号：US14971370

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj R. Sastry ,  Solmaz Ghaznavi ,  Julien Carreno ,  Padraig J. Kearney

IPC: H04L9/32 ,  H04L9/06 ,  H04L29/06

CPC classification number: H04L9/3239 ,  G06F21/75 ,  G06F21/85 ,  G09C1/00 ,  H04L9/0643 ,  H04L63/061 ,  H04L63/123 ,  H04L2209/26

Abstract: System and techniques for secure unlock to access debug hardware are described herein. A cryptographic key may be received at a hardware debug access port of a device. A digest may be computed from the cryptographic key at an unlock unit of the device. A fuse value may be received from a non-volatile read-only storage on the device. The digest and the fuse value may be compared to determine whether they are the same. A pass-fail pulse may be provided that indicates the result of the comparing.

公开(公告)号：US12124616B2

公开(公告)日：2024-10-22

申请号：US17830225

申请日：2022-06-01

Applicant: Intel Corporation

Inventor： Claire Vishik ,  Reshma Lal ,  Santosh Ghosh

IPC: G06F21/64 ,  G06F16/14 ,  G06F21/60

CPC classification number: G06F21/64 ,  G06F21/602 ,  G06F16/152

Abstract: A system and method of enhancing the trustworthiness of an artificial intelligence system include detecting whether a data element includes an existing data domain tag, processing the data element into a transformed data element, generating a data domain tag, where the data domain tag includes at least a data domain identifier and a timestamp, appending the data domain tag to the transformed data element, creating a signature for the transformed data element and the appended data domain tag using a private key, and creating another signature for the data domain tag using the private key.

公开(公告)号：US20240264837A1

公开(公告)日：2024-08-08

申请号：US18164738

申请日：2023-02-06

Applicant: Intel Corporation

Inventor： Christoph Dobraunig ,  Santosh Ghosh ,  Manoj Sastry

IPC: G06F9/30

CPC classification number: G06F9/30196 ,  G06F9/30029 ,  G06F9/30032

Abstract: Techniques are described for an instruction for a conditional rotate and XOR operation in a single instruction and triple input bitwise logical operations in a single instruction in an instruction set of a computing system.

公开(公告)号：US12050701B2

公开(公告)日：2024-07-30

申请号：US17833515

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Michael E. Kounavis ,  Santosh Ghosh ,  Sergej Deutsch ,  Michael LeMay ,  David M. Durham

IPC: G06F21/60 ,  G06F9/30 ,  G06F9/32 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/14 ,  G06F21/12 ,  G06F21/62 ,  G06F21/72 ,  G06F21/79 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14

CPC classification number: G06F21/602 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30178 ,  G06F9/321 ,  G06F9/45558 ,  G06F9/48 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0646 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1408 ,  G06F12/1458 ,  G06F12/1466 ,  G06F21/12 ,  G06F21/6227 ,  G06F21/72 ,  G06F21/79 ,  H04L9/0637 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/0869 ,  H04L9/0894 ,  H04L9/14 ,  G06F2009/45587 ,  G06F2212/1052 ,  H04L2209/125

Abstract: Technologies disclosed herein provide cryptographic computing. An example method comprises executing a first instruction of a first software entity to receive a first input operand indicating a first key associated with a first memory compartment of a plurality of memory compartments stored in a first memory unit, and execute a cryptographic algorithm in a core of a processor to compute first encrypted contents based at least in part on the first key. Subsequent to computing the first encrypted contents in the core, the first encrypted contents are stored at a memory location in the first memory compartment of the first memory unit. More specific embodiments include, prior to storing the first encrypted contents at the memory location in the first memory compartment and subsequent to computing the first encrypted contents in the core, moving the first encrypted contents into a level one (L1) cache outside a boundary of the core.

公开(公告)号：US12047514B2

公开(公告)日：2024-07-23

申请号：US17732852

申请日：2022-04-29

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj Sastry ,  Prakash Iyer ,  Ting Lu

IPC: H04L9/32 ,  G06F7/72 ,  H04L9/06 ,  H04L9/30

CPC classification number: H04L9/3247 ,  G06F7/725 ,  H04L9/0643 ,  H04L9/3066 ,  H04L9/3234 ,  H04L9/3236 ,  H04L9/3252

Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.

公开(公告)号：US20240211261A1

公开(公告)日：2024-06-27

申请号：US18145776

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Christoph Dobraunig ,  Manoj Sastry

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30029 ,  G06F9/30032

Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction, and executing, by execution circuitry, to execute the decoded XOR3P instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR, and store the rotated XOR result.