公开(公告)号：US11074204B2

公开(公告)日：2021-07-27

申请号：US16369277

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar

IPC: G06F13/24

Abstract: A processor includes cores to execute instructions, and circuitry to detect a system management interrupt (SMI) event on the processor, direct an indication of the SMI event to an arbiter on a controller hub, and receive an interrupt signal from the arbiter. The processor also includes an SMI handler to take action in response to the interrupt, and circuitry to communicate the interrupt signal to the cores. The cores include circuitry to pause while the SMI handler responds to the interrupt. The interrupt handler includes circuitry to determine that a second SMI event detected on the processor or controller hub is pending, and to take action in response. The interrupt handler includes circuitry to set an end-of-SMI bit to indicate that the interrupt handler has completed its actions. The controller includes circuitry to prevent the arbiter from issuing another interrupt to the processor while this bit is false.

公开(公告)号：US20210209052A1

公开(公告)日：2021-07-08

申请号：US17041519

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Zhi Yong Chen ,  Sarathy Jayakumar ,  Yi Zeng ,  Wenjuan Mao ,  Anil Agrawal

IPC: G06F13/40 ,  G06F9/4401

Abstract: There is disclosed in one example a multi-core computing system configured to provide a hot-swappable CPU0, including: a first CPU in a first CPU socket and a second CPU in a second CPU socket; a switch including a first media interface to the first CPU socket and a second media interface to the second CPU socket; and one or more mediums including non-transitory instructions to detect a hot swap event of the first CPU, designate the second CPU as CPU0, determine that a new CPU has replaced the first CPU, operate the switch to communicatively couple the new CPU to a backup initialization code store via the first media interface, initialize the new CPU, and designate the new CPU as CPUN, wherein N≠0.

公开(公告)号：US10649690B2

公开(公告)日：2020-05-12

申请号：US14998196

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  George Vergis ,  Sarathy Jayakumar

IPC: G06F11/00 ,  G06F3/06 ,  G06F13/16 ,  G06F21/14 ,  G06F21/53 ,  G06F13/28

Abstract: In an example, there is disclosed a memory controller, including: a data buffer to drive a determinate value to a data bus to communicatively couple to a memory; and a register clock driver to: receive a memory initialization command from a processor; and incrementally step through a plurality of initialization addresses, sequentially driving each initialization address to an address bus to communicatively couple to the memory. There is also disclosed a computing device comprising the memory controller, and a method of initializing memory comprising incrementally stepping through a plurality of initialization addresses and sequentially writing a determinate value to each address.

公开(公告)号：US10474596B2

公开(公告)日：2019-11-12

申请号：US14749893

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Ashok Raj ,  John G. Holm ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Sergiu D. Ghetie

IPC: G06F13/24 ,  G06F1/3287 ,  G06F9/4401 ,  G06F1/3228

Abstract: In one embodiment, a processor includes a plurality of cores including a first core to be reserved for execution in a protected domain, the first core to be hidden from an operating system. The processor may further include a filter coupled to the plurality of cores, where the filter includes a plurality of fields each associated with one of the plurality of cores to indicate whether an interrupt of the protected domain is to be directed to the corresponding core. Other embodiments are described and claimed.

公开(公告)号：US10296416B2

公开(公告)日：2019-05-21

申请号：US15201438

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US10162761B2

公开(公告)日：2018-12-25

申请号：US15465560

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Sreenivas Mandava ,  Sarathy Jayakumar ,  Mohan J Kumar ,  Theodros Yigzaw ,  Ronald N Story

IPC: G06F12/02 ,  G06F12/06 ,  G06F12/1009 ,  G06F9/26 ,  G06F9/30 ,  G06F13/24 ,  G06F13/364

Abstract: An apparatus and method are described for system physical address to memory module address translation. For example, one embodiment of an apparatus comprises: a fetch circuit of a core to fetch a system physical address (SPA) translate instruction from memory; a decode circuit of the core to decode the SPA translate instruction; a first register to store an SPA associated with the SPA translate instruction; a memory controller comprising one or more channel controllers to initiate a translation using the SPA, the memory controller to transmit a translation request to a first channel controller; the first channel controller to synthesize a response including dual in-line memory module (DIMM) address information; and a second register to store the DIMM address information to be used to identify the DIMM during subsequent memory transactions.

公开(公告)号：US12164906B2

公开(公告)日：2024-12-10

申请号：US16801382

申请日：2020-02-26

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Sarathy Jayakumar ,  Chuan Song ,  Ruixia Li ,  Siyuan Fu ,  Jiaxin Wu ,  Lui He

IPC: G06F8/656 ,  G06F8/654 ,  G06F21/57

Abstract: A modular microcode (uCode) patch method to support runtime persistent update and associated apparatus. The method enables BIOS uCode patches to be received during platform runtime operations and written to first and second uCode extension regions as uCode images for a firmware device layout that further includes a uCode base region in which a current uCode image is stored. Following a platform reset, the first and second uCode extension regions are inspected to determine if one or more valid and newer uCode images (than the current uCode image) are present. If so, the newest uCode image is booted rather than the current uCode image. Following a successful boot, the newest uCode image is copied to the uCode base region to sync-up the current uCode image to the newest version. In one aspect, received uCode images are written to the first and second uCode extension regions in an alternating manner to support roll-back.

公开(公告)号：US11307996B2

公开(公告)日：2022-04-19

申请号：US16206516

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Ashok Raj ,  Wei P. Chen ,  Theodros Yigzaw ,  John Holm

IPC: G06F12/1027 ,  G06F12/0864 ,  G06F13/16 ,  G06F11/22 ,  G06F9/38

Abstract: In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.

公开(公告)号：US20210365559A1

公开(公告)日：2021-11-25

申请号：US17392012

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Jiewen Yao ,  Murugasamy Nachimuthu ,  Ruixia Li ,  Siyuan Fu ,  Chuan SONG ,  Wei Xu

IPC: G06F21/57

Abstract: Methods and apparatus for seamless system management mode (SMM) code injection. A code injection listener is installed in BIOS during booting of the computer system or platform. During operating system (OS) runtime operation a secure execution mode code injection image comprising injected code is received and delivered to the BIOS. The processor execution mode is switched to a secure execution mode such as SMM, and while in the secure execution mode the injected code is accessed and executed on the processor to effect one or more changes such as patching processor microcode, a profile or policy reconfiguration, and a security fix. The solution enables platform changes to be effected during OS runtime without having to reboot the system.

公开(公告)号：US11138072B2

公开(公告)日：2021-10-05

申请号：US15852021

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Sarathy Jayakumar ,  Sergiu D. Ghetie ,  Neeraj Upasani ,  Ronald N. Story

IPC: G06F11/14 ,  G06F11/07

Abstract: There is disclosed in one example a processor, including: a protected runtime mode (PRM) module to receive a PRM interrupt and to: suspend operation of a software task executing on the processor; save processor state information; place the microprocessor into PRM; access a PRM handler in a designated PRM memory region, wherein the PRM handler comprises a platform specific task; restore the processor state; and resume operation of the software task.