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    Synthesized clock synchronization between network devices
    21.
    发明授权
    Synthesized clock synchronization between network devices 有权

    公开(公告)号：US11283454B2

    公开(公告)日：2022-03-22

    申请号：US16920772

    申请日：2020-07-06

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Ran Ravid ,  Aviv Berg ,  Lavi Koch ,  Chen Gaist ,  Dotan David Levi

    IPC: H03L7/08 ,  G06F1/12 ,  H04L7/033 ,  H03L7/099

    Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.

    Communication with accelerator via RDMA-based network adapter
    23.
    发明授权
    Communication with accelerator via RDMA-based network adapter 有权

    公开(公告)号：US11184439B2

    公开(公告)日：2021-11-23

    申请号：US16827912

    申请日：2020-03-24

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Haggai Eran ,  Dotan David Levi ,  Maxim Fudim ,  Liran Liss

    IPC: H04L29/08 ,  G06F13/28 ,  G06F15/173

    Abstract: A network node includes a bus switching element, and a network adapter, an accelerator and a host, all coupled to communicate via the bus switching element. The network adapter is configured to communicate with remote nodes over a communication network. The host is configured to establish a RDMA link between the accelerator and the RDMA endpoint by creating a Queue Pair (QP) to be used by the accelerator for communication with the RDMA endpoint via the RDMA link. The accelerator is configured to exchange data, via the network adapter, between a memory of the accelerator and a memory of the RDMA endpoint.

    Network Adapter with Time-Aware Packet-Processing Pipeline
    25.
    发明申请
    Network Adapter with Time-Aware Packet-Processing Pipeline 有权

    公开(公告)号：US20210243140A1

    公开(公告)日：2021-08-05

    申请号：US16782075

    申请日：2020-02-05

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula

    IPC: H04L12/861 ,  H04L29/06 ,  H04L12/741 ,  H04L12/46 ,  H04L12/931 ,  H04L12/801 ,  H04W56/00

    Abstract: A network adapter includes a host interface configured to communicate with a host, a network interface configured to communicate with a communication network, and packet processing circuitry. The packet processing circuitry is configured to receive a packet from the host via the host interface, or from the communication network via the network interface, to receive an indication of a network time used for synchronizing network elements in the communication network, to match the packet to a rule, the rule including a condition and an action, and to perform the action in response to the packet meeting the condition, wherein one or more of (i) the condition in the rule and (ii) the action in the rule, depend on the network time.

    Direct Packet Placement
    27.
    发明申请
    Direct Packet Placement 审中-公开

    公开(公告)号：US20200092229A1

    公开(公告)日：2020-03-19

    申请号：US16693302

    申请日：2019-11-24

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Avi Urman

    IPC: H04L12/939 ,  H04L12/861 ,  H04L12/879 ,  H04L29/06 ,  H04W28/04

    Abstract: Communication apparatus includes a host interface and a network interface, which receives from a packet communication network at least one packet stream including a sequence of data packets, which include headers containing respective sequence numbers and data payloads containing slices of the data segment having a predefined, fixed size per slice. Packet processing circuitry is configured to receive the data packets from the network interface, and to map the data payloads of the data packets in the at least one packet stream, using a linear mapping of the sequence numbers, to respective addresses in the buffer.

    CLOCK SYNCHRONIZATION BETWEEN NETWORKED DEVICES BASED ON PACKET CONGESTION INFORMATION
    29.
    发明申请
    CLOCK SYNCHRONIZATION BETWEEN NETWORKED DEVICES BASED ON PACKET CONGESTION INFORMATION 有权

    公开(公告)号：US20250023705A1

    公开(公告)日：2025-01-16

    申请号：US18219895

    申请日：2023-07-10

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Wojciech Wasko ,  Dotan David Levi ,  Thomas Kernen

    IPC: H04L7/00

    Abstract: A network device includes control logic coupled to a receiver. The control logic detects an synchronization packet received via the receiver from a second network device over a network that is precision time protocol unaware. The control logic determines that a portion of the synchronization packet is asserted, indicating that the synchronization packet has incurred congestion traversing the network. The control logic adjusts, based on an assertion of the portion, a weight applied to timestamps associated with sending and receiving the synchronization packet in performing clock synchronization with the second network device.

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