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    SYSTEM AND METHOD OF SELECTIVELY APPLYING NEGATIVE VOLTAGE TO WORDLINES DURING MEMORY DEVICE READ OPERATION
    22.
    发明公开
    SYSTEM AND METHOD OF SELECTIVELY APPLYING NEGATIVE VOLTAGE TO WORDLINES DURING MEMORY DEVICE READ OPERATION 审中-公开
    系统和方法阅读过程中的存储设备在负张力开字线中的选择性应用

    公开(公告)号：EP2232494A1

    公开(公告)日：2010-09-29

    申请号：EP09701299.1

    申请日：2009-01-09

    Applicant: QUALCOMM Incorporated

    Inventor： YOON, Sei, Seung ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed, H.

    IPC: G11C11/16

    CPC classification number: G11C8/08 ,  G11C11/1673

    Abstract: Systems and methods of selectively applying negative voltage to word lines during memory device read operation are disclosed. In an embodiment, a memory device (100) includes a word line logic circuit (110) coupled to a plurality of word lines (108) and adapted to selectively apply a positive voltage (V) to a selected word line coupled to a selected memory cell that includes a magnetic tunnel junction (MTJ) device and to apply a negative voltage (NV) to unselected word lines.

    Abstract translation: 存储器装置读出在外科手术期间施加到字线负电压的系统和选择性的方法是游离缺失盘。 ，实施例中的存储装置包括耦合到字线和angepasst多个A字线逻辑电路以选择性地施加正电压到耦合到选定存储器单元的选定字线确实包括磁性隧道结（MTJ）装置和 负电压施加到未选字线。

    DIGITALLY-CONTROLLABLE DELAY FOR SENSE AMPLIFIER
    25.
    发明公开
    DIGITALLY-CONTROLLABLE DELAY FOR SENSE AMPLIFIER 有权
    WITH DIGITAL DELAY应税检测放大器

    公开(公告)号：EP2374129A1

    公开(公告)日：2011-10-12

    申请号：EP09793651.2

    申请日：2009-12-07

    Applicant: QUALCOMM Incorporated

    Inventor： PARK, Dongkyu ,  DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  ABU-RAHMA, Mohamed Hassan Soliman ,  YOON, Sei Seung

    IPC: G11C7/06 ,  G11C7/22 ,  G11C11/16

    CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2207/065 ,  G11C2207/2281

    Abstract: Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. A circuit includes a sense amplifier (160), having a first input (162), a second input (164), and an enable input (166); a first amplifier (132) coupled to an output of a magnetic resistance-based memory cell (112); a second amplifier (134) coupled to a reference output of the cell; and a digitally-controllable amplifier (136) coupled to a tracking circuit cell (116) that is similar to the cell of the MRAM. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit (150). The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal (152) from the digitally-controllable amplifier via the logic circuit.

    MEMORY DEVICE FOR RESISTANCE-BASED MEMORY APPLICATIONS
    26.
    发明公开
    MEMORY DEVICE FOR RESISTANCE-BASED MEMORY APPLICATIONS 有权
    存储设备电阻式存储器应用

    公开(公告)号：EP2332142A1

    公开(公告)日：2011-06-15

    申请号：EP09792136.5

    申请日：2009-09-01

    Applicant: QUALCOMM Incorporated

    Inventor： DAVIERWALLA, Anosh B. ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed Hassan ,  SANI, Mehdi Hamidi ,  YOON, Sei Seung

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C11/16

    CPC classification number: G11C11/1673

    Abstract: In a particular embodiment, a memory device (100) is disclosed that includes a memory cell (226) including a resistance based memory element (228) coupled to an access transistor (230). The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier (202) configured to couple the memory cell to a supply voltage (Vamp) that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor (216) that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.

    MRAM DEVICE WITH SHARED SOURCE LINE
    27.
    发明公开
    MRAM DEVICE WITH SHARED SOURCE LINE 有权
    具有共同使用的源LINE MRAM安排

    公开(公告)号：EP2245630A1

    公开(公告)日：2010-11-03

    申请号：EP08861010.0

    申请日：2008-12-19

    Applicant: QUALCOMM Incorporated

    Inventor： YOON, Sei, Seung ,  ZHONG, Cheng ,  PARK, Dongkyu ,  ABU-RAHMA, Mohamed, H.

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673

    Abstract: In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source line coupled to the first memory cell and coupled to the second memory cell. The memory cell may be formed by spin transfer torque magnetoresistive memory cells having selection field effect transistors. The memory cell may also be formed as complementary cell pairs. Half-selected cells are supplied with or across them to prevent read disturb.

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