公开(公告)号：US20210099197A1

公开(公告)日：2021-04-01

申请号：US17039775

申请日：2020-09-30

Applicant: Qualcomm Incorporated

Inventor： Chuan Wang ,  Li Liu ,  Kevin Hsi-Huai Wang ,  Bhushan Shanti Asuri ,  Kang Yang ,  Shrenik Patel

IPC: H04B1/401

Abstract: An apparatus is disclosed for transceiving signals in multiple modes. In example implementations, an apparatus includes a transceiver that includes a first amplifier; a mixer having at least one input node and at least one output node, with the at least one input node coupled to the first amplifier; and a second amplifier coupled to the at least one output node of the mixer. The transceiver also includes a first register coupled to the first amplifier and a second register coupled to the second amplifier. The transceiver further includes at least one memory realizing a lookup table. The at least one memory is coupled to the first register and the second register. The lookup table includes a first portion corresponding to a first mode of the transceiver and a second portion corresponding to a second mode of the transceiver.

公开(公告)号：US20180139078A1

公开(公告)日：2018-05-17

申请号：US15472454

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Ayush Mittal ,  Bhushan Shanti Asuri ,  Krishnaswamy Thiagarajan ,  Sameer Vasantlal Vora ,  Mahim Ranjan

IPC: H04L25/03

CPC classification number: H04L25/03 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0082 ,  H03D2200/0086 ,  H03H7/21 ,  H03H2007/013 ,  H04B1/0475 ,  H04L25/03828 ,  H04L27/36

Abstract: A system includes: a baseband phase generator configured to receive differential in-phase (I) and quadrature (Q) signals and configured to output N phase-shifted baseband signals, wherein N is greater than 4, further wherein the baseband phase generator comprises a plurality of notch filters configured to receive the I and Q signals; and an upconverter configured to receive the phase-shifted baseband signals, to perform mixing on the phase-shifted baseband signals, and to output a differential upconverted signal.

公开(公告)号：US20160241211A1

公开(公告)日：2016-08-18

申请号：US14620823

申请日：2015-02-12

Applicant: QUALCOMM Incorporated

Inventor： Muhammad Hassan ,  Bhushan Shanti Asuri ,  Apsara Ravish Suvarna ,  Youngchang Yoon

IPC: H03F3/45 ,  H03F1/22

CPC classification number: H03F3/45632 ,  H03F1/223 ,  H03F3/245 ,  H03F3/45188 ,  H03F2200/09 ,  H03F2200/378 ,  H03F2203/45024 ,  H03F2203/45082 ,  H03F2203/45084 ,  H03F2203/45204 ,  H03F2203/45481 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45706 ,  H03F2203/45731

Abstract: A differential amplifier having a tunable filter is disclosed. The tunable filter may attenuate some common-mode signals while not affecting amplification of differential signals. The tunable filter may include a resonant circuit to select frequencies of common-mode signals to attenuate. The resonant circuit may include a variable capacitor series-coupled to an inductor. A resonant frequency of the resonant circuit may be determined, in part, by a capacitance value of the variable capacitor.

Abstract translation: 公开了一种具有可调谐滤波器的差分放大器。 可调谐滤波器可以衰减一些共模信号，而不影响差分信号的放大。 可调滤波器可以包括谐振电路，以选择共模信号的频率来衰减。 谐振电路可以包括串联耦合到电感器的可变电容器。 谐振电路的谐振频率可以部分地由可变电容器的电容值确定。

公开(公告)号：US20150372702A1

公开(公告)日：2015-12-24

申请号：US14476536

申请日：2014-09-03

Applicant: QUALCOMM Incorporated

Inventor： Bhushan Shanti Asuri ,  Shrenik Patel ,  Chiewcharn Narathong

IPC: H04B1/10 ,  H04B1/12 ,  H04B1/40

CPC classification number: H04B1/1027 ,  H04B1/10 ,  H04B1/12 ,  H04B1/40 ,  H04B1/406 ,  H04B2001/1072

Abstract: An apparatus includes a first filter tuned to a sub-band of a frequency band and a second filter tuned to the frequency band. The first filter is configured to be coupled to a receiver based on a first mode. The second filter is configured to be coupled to the receiver based on a second mode.

Abstract translation: 一种装置包括调谐到频带的子带的第一滤波器和调谐到该频带的第二滤波器。 第一滤波器被配置为基于第一模式耦合到接收器。 第二滤波器被配置为基于第二模式耦合到接收器。

公开(公告)号：US20150349907A1

公开(公告)日：2015-12-03

申请号：US14513003

申请日：2014-10-13

Applicant: QUALCOMM Incorporated

Inventor： Chiewcharn Narathong ,  Lai Kan Leung ,  Dongling Pan ,  Rajagopalan Rangarajan ,  Kevin Hsi-huai Wang ,  Bhushan Shanti Asuri ,  Yiwu Tang

IPC: H04J4/00 ,  H04B1/3827 ,  H04L5/14 ,  H04W88/02

CPC classification number: H04J4/00 ,  H04B1/0082 ,  H04B1/3833 ,  H04B1/403 ,  H04B1/50 ,  H04B1/54 ,  H04B7/00 ,  H04L5/001 ,  H04L5/0023 ,  H04L5/14 ,  H04L5/1469 ,  H04L7/00 ,  H04L27/36 ,  H04L27/38 ,  H04W88/02

Abstract: Reconfiguring a transceiver design using a plurality of frequency synthesizers and a plurality of carrier aggregation (CA) receiver (Rx) and transmitter (Tx) chains, the method including: connecting a first frequency synthesizer to a first CA Tx chain; connecting the plurality of frequency synthesizers to the plurality of CA Rx chains, wherein a second frequency synthesizer of the plurality of frequency synthesizers is connected as a shared synthesizer to a first CA Rx chain and a second CA Tx chain.

Abstract translation: 使用多个频率合成器和多个载波聚合（CA）接收机（Rx）和发射机（Tx）链重新配置收发器设计，所述方法包括：将第一频率合成器连接到第一CA Tx链; 将多个频率合成器连接到多个CA Rx链，其中多个频率合成器中的第二频率合成器作为共享合成器连接到第一CA Rx链和第二CA Tx链。

公开(公告)号：US09112748B2

公开(公告)日：2015-08-18

申请号：US13765667

申请日：2013-02-12

Applicant: QUALCOMM Incorporated

Inventor： Bhushan Shanti Asuri ,  Shrenik Patel

IPC: H04L25/08 ,  H04B1/04

CPC classification number: H04L25/08 ,  H04B1/0475

Abstract: An apparatus for reducing spurs is described. The apparatus includes a coarse digital to analog converter (DAC). The apparatus also includes a correction term generator. The correction term generator generates a correction term. The correction term has an amplitude within a dynamic range of the coarse digital to analog converter (DAC). The apparatus also includes a baseband filter. The correction term is selected such that the baseband filter reduces the correction term to an amplitude approximating that of a spur in a transmit signal. The correction term is used to reduce a spur.

Abstract translation: 描述了用于减少杂散的装置。 该装置包括粗略的数模转换器（DAC）。 该装置还包括校正项发生器。 校正项发生器产生校正项。 校正项具有在粗略数模转换器（DAC）的动态范围内的振幅。 该装置还包括基带滤波器。 校正项被选择为使得基带滤波器将校正项减小到接近发射信号中的杂波的幅度。 修正项用于减少刺激。

公开(公告)号：US12301170B2

公开(公告)日：2025-05-13

申请号：US17481559

申请日：2021-09-22

Applicant: QUALCOMM INCORPORATED

Inventor： Chuan Wang ,  Li Liu ,  Bhushan Shanti Asuri ,  Gurkanwal Singh Sahota ,  Abdellatif Bellaouar ,  Vinod Panikkath

IPC: H03F1/02 ,  H03F3/21 ,  H03F3/24 ,  H04B1/405

Abstract: A transceiver interface for a phased array element includes a first magnetic circuit having a primary coil and a secondary coil, a second magnetic circuit having a primary coil, a secondary coil and a tertiary coil, a main amplifier path and an auxiliary amplifier path, the main amplifier path coupled to the primary coil of the second magnetic circuit and configured to receive a quadrature signal, the main amplifier path configured to provide a quadrature output signal, the auxiliary amplifier path coupled to the primary coil of the first magnetic circuit and configured to receive an in-phase signal, the auxiliary amplifier path configured to provide an in-phase output signal, a selectable output circuit configured to selectively combine the in-phase output signal and the quadrature output signal, and a low noise amplifier (LNA) coupled to the tertiary coil of the second magnetic circuit.

公开(公告)号：US11990876B2

公开(公告)日：2024-05-21

申请号：US17478431

申请日：2021-09-17

Applicant: QUALCOMM INCORPORATED

Inventor： Yung-Chung Lo ,  Hyejeong Song ,  Bhushan Shanti Asuri ,  Sahar Nozari

IPC: H04B1/40 ,  H03F1/02 ,  H03F3/193 ,  H03F3/21 ,  H03F3/24

CPC classification number: H03F3/245 ,  H03F1/0211 ,  H04B1/40 ,  H03F2200/294 ,  H03F2200/451

Abstract: A transceiver interface circuit, comprising a driver amplifier (DA), a load line impedance modulation circuit coupled to the DA; and multiple selectable output ports coupled to the load line impedance modulation circuit, an impedance presented by the load line impedance modulation circuit being adjustable dependent on at least a number of output ports coupled to the load line impedance modulation circuit.

公开(公告)号：US11736071B2

公开(公告)日：2023-08-22

申请号：US17208864

申请日：2021-03-22

Applicant: QUALCOMM Incorporated

Inventor： Ayush Mittal ,  Sreenivasa Mallia ,  Arpit Gupta ,  Krishnaswamy Thiagarajan ,  Bhushan Shanti Asuri

IPC: H03F1/22 ,  H03F1/42 ,  H03F3/24

CPC classification number: H03F1/42 ,  H03F3/245 ,  H03F2200/09 ,  H03F2200/36 ,  H03F2200/451

Abstract: Certain aspects of the present disclosure provide an amplifier. The amplifier generally includes an amplifier core circuit configured to amplify a radio frequency signal and having a first output and a second output; a transformer coupled to the amplifier core circuit, the transformer having a primary winding and a secondary winding, the primary winding being coupled to the first output and the second output of the amplifier core circuit, the secondary winding being coupled to an output node of the amplifier; and a variable resistance circuit coupled in parallel with the primary winding.

公开(公告)号：US11367697B2

公开(公告)日：2022-06-21

申请号：US16875972

申请日：2020-05-15

Applicant: QUALCOMM Incorporated

Inventor： Ibrahim Ramez Chamas ,  Mohamed Abouzied ,  Bhushan Shanti Asuri

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/58 ,  H03H7/42 ,  H04B1/40

Abstract: An RF flip chip is provided in which a local bump region adjacent a die corner includes a balun having a centrally-located bump.