公开(公告)号：WO2009067590A1

公开(公告)日：2009-05-28

申请号：PCT/US2008/084181

申请日：2008-11-20

Applicant: QUALCOMM Incorporated ,  VENKUMAHANTI, Suresh K ,  CODRESCU, Lucian ,  KRITHIVASAN, Shankar ,  SHEN, Jian ,  WANG, Lin

Inventor： VENKUMAHANTI, Suresh K ,  CODRESCU, Lucian ,  KRITHIVASAN, Shankar ,  SHEN, Jian ,  WANG, Lin

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30101 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30141 ,  G06F9/3016 ,  G06F9/3824

Abstract: In a particular embodiment, a method is disclosed that includes identifying a first block of bits within a result to be written to a destination register by an execution unit. The result includes a plurality of bits having the first block of bits and a second block of bits. The first block of bits has a value of zero. The method further includes providing an encoded bit value representing the first block of bits to a control register and selectively writing the second block of bits, but not the first block of bits, to the destination register. The destination register is sized to receive the first and second blocks of bits.

Abstract translation: 在特定实施例中，公开了一种方法，其包括通过执行单元识别要写入到目的地寄存器的结果内的第一比特块。 结果包括具有第一比特块和第二比特块的多个比特。 第一个位块的值为零。 该方法还包括向控制寄存器提供表示第一比特位的编码比特值，并将第二比特块而不是第一比特块写入目的寄存器。 目的地寄存器的大小适于接收第一和第二位块。

公开(公告)号：WO2009032936A1

公开(公告)日：2009-03-12

申请号：PCT/US2008/075270

申请日：2008-09-04

Applicant: QUALCOMM Incorporated ,  INGLE, Ajay Anant ,  CODRESCU, Lucian ,  VENKUMAHANTI, Suresh

Inventor： INGLE, Ajay Anant ,  CODRESCU, Lucian ,  VENKUMAHANTI, Suresh

IPC: G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3867

Abstract: A device is disclosed that includes an instruction execution pipeline having multiple stages for executing an instruction. The device also includes a control logic circuit coupled to the instruction execution pipeline. The control logic circuit is adapted to skip at least one stage of the instruction execution pipeline during execution of the instruction. The control logic circuit is also adapted to execute at least one non-skipped stage during execution of the decoded instruction.

Abstract translation: 公开了一种包括具有用于执行指令的多个级的指令执行流水线的装置。 该装置还包括耦合到指令执行管线的控制逻辑电路。 控制逻辑电路适于在执行指令期间跳过指令执行流水线的至少一个级。 控制逻辑电路还适于在执行解码的指令期间执行至少一个非跳过级。

公开(公告)号：WO2007134013A2

公开(公告)日：2007-11-22

申请号：PCT/US2007/068394

申请日：2007-05-07

Applicant: QUALCOMM Incorporated ,  ZENG, Mao ,  CODRESCU, Lucian

Inventor： ZENG, Mao ,  CODRESCU, Lucian

IPC: G06F9/315

CPC classification number: G06F9/30032 ,  G06F9/30025 ,  G06F9/30036

Abstract: A method and system to combine corresponding half word units from multiple register units within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to combine predetermined disparate source register units from a register file structure is received within a processing unit. The instruction is then executed to combine corresponding half word units from the source register units and to input the half word units into respective portions of a resulting destination register unit. During the execution of the instruction, the predetermined source register units are identified and corresponding most significant half word units and associated data are retrieved from the identified register units. The retrieved half word units are further combined and input into a respective most significant portion of a resulting destination register unit. Similarly, corresponding least significant half word units and associated data are retrieved from the identified register units. The retrieved half word units are further combined and input into a respective least significant portion of a resulting destination register unit. Finally, the resulting destination register unit is stored into the register file structure for further processing.

Abstract translation: 描述了在执行单个指令期间组合微处理器内的多个寄存器单元（例如数字信号处理器）的相应半字单元的方法和系统。 在处理单元内接收从寄存器文件结构组合预定的不同的源寄存器单元的指令。 然后执行指令以组合来自源寄存器单元的对应的半字单元，并将半字单元输入到所得到的目标寄存器单元的相应部分。 在执行指令期间，识别预定的源寄存器单元，并且从所识别的寄存器单元检索对应的最高有效半字单元和相关联的数据。 所获取的半字单元被进一步组合并输入到所得到的目标寄存器单元的相应最高有效部分。 类似地，从所识别的寄存器单元检索相应的最低有效半字单元和相关数据。 所检索的半字单元被进一步组合并输入到所得到的目标寄存器单元的相应的最低有效部分。 最后，将所得到的目标寄存器单元存储到寄存器文件结构中以进一步处理。

公开(公告)号：WO2007134011A3

公开(公告)日：2007-11-22

申请号：PCT/US2007/068389

申请日：2007-05-07

Applicant: QUALCOMM INCORPORATED ,  ZENG, Mao ,  CODRESCU, Lucian

Inventor： ZENG, Mao ,  CODRESCU, Lucian

IPC: H04N7/36 ,  G06F9/302

Abstract: Method and apparatus for performing two independent sum-of-absolute-difference (SAD) operations when receiving a single instruction (505, 705) is provided. The two operations may be performed in parallel. The operations process values stored in two source registers (405, 410) and the results are stored to a destination register (425). The source and destination registers each have two independently accessible sections, whereby a first SAD operation (401) can access a first section while a second independent SAD operation (402) can simultaneously access a second section of the register. The first SAD operation is performed on values in a first section of the source registers, the result being stored to a first section of the destination register. The second SAD operation is performed on values in a second section of the source registers, the result being stored to a second section of the destination register. The values may comprise pixel values.

公开(公告)号：WO2007047784A3

公开(公告)日：2007-04-26

申请号：PCT/US2006/040759

申请日：2006-10-18

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  ANDERSON, William, C.

Inventor： CODRESCU, Lucian ,  ANDERSON, William, C.

IPC: G06F9/38 ,  G06F9/48 ,  G06F9/30

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system process interrupts arising in a multithreaded processor by receiving in an interrupt register a plurality of interrupts of a statistically indeterminate interrupt type and then associating a plurality of processing threads with the interrupt register for receiving the interrupt from the interrupt register. The method and system mask at least a subset of the plurality of processing threads so as to receive within each of the threads within the subset only ones of the plurality of interrupts of one or more predetermined types, thereby controlling on a per thread basis the processing of the plurality of interrupts according to the mask associated with a particular thread.

公开(公告)号：WO2007008749A3

公开(公告)日：2007-01-18

申请号：PCT/US2006/026662

申请日：2006-07-07

Applicant: QUALCOMM Incorporated ,  CODRESCU, Lucian ,  PADGETT, Donald, Robert ,  PLONDKE, Erich ,  SIMPSON, Taylor ,  AHMED, Muhammad ,  ANDERSON, William, C. ,  JAMIL, Sujat

Inventor： CODRESCU, Lucian ,  PADGETT, Donald, Robert ,  PLONDKE, Erich ,  SIMPSON, Taylor ,  AHMED, Muhammad ,  ANDERSON, William, C. ,  JAMIL, Sujat

IPC: G06F9/38 ,  G06F1/32 ,  G06F9/46

Abstract: A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first of the plurality of executable program threads and a second data field to control a second execution mode of a second of the plurality of executable program threads. In a particular embodiment, the first execution mode is a run mode and the second execution mode is a low power mode.

公开(公告)号：WO2006110905A3

公开(公告)日：2006-10-19

申请号：PCT/US2006/014173

申请日：2006-04-11

Applicant: QUALCOMM INCORPORATED ,  AHMED, Muhammad ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  ANDERSON, William C.

Inventor： AHMED, Muhammad ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  ANDERSON, William C.

IPC: G06F9/38

Abstract: A processor device is disclosed and includes a memory unit and at least one interleaved multi-threading instruction pipeline. The interleaved multi-threading instruction pipeline utilizes a number of clock cycles that is less than an instruction issue rate for each of a plurality of program threads that are stored within the memory unit. The memory unit includes six instruction caches. Further, the processor device includes six register files and each of the six register files is associated with one of the six instruction caches. Each of the plurality of program threads is associated with one of the six register files. Further, each of the six program threads includes a plurality of instructions and each of the plurality of instructions is stored within one of the six instruction caches of the memory.

公开(公告)号：WO2006110886A2

公开(公告)日：2006-10-19

申请号：PCT/US2006/013948

申请日：2006-04-11

Applicant: QUALCOMM Incorporated ,  AHMED, Muhammad ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  ANDERSON, William C. ,  LESTER, Robert Allan ,  JONES, Phillip M.

Inventor： AHMED, Muhammad ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  ANDERSON, William C. ,  LESTER, Robert Allan ,  JONES, Phillip M.

CPC classification number: G06F9/325 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/381

Abstract: An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.

Abstract translation: 指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。 如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。 第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从 如果目标指令没有存储在第二存储器结构中的第一存储器结构。

公开(公告)号：WO2006102668A3

公开(公告)日：2006-09-28

申请号：PCT/US2006/011175

申请日：2006-03-23

Applicant: QUALCOMM INCORPORATED ,  AHMED, Muhammad ,  JAMIL, Sujat ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  ANDERSON, William C.

Inventor： AHMED, Muhammad ,  JAMIL, Sujat ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  ANDERSON, William C.

IPC: G06F9/38

Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method furtherswitches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.

公开(公告)号：WO2006102664A2

公开(公告)日：2006-09-28

申请号：PCT/US2006/011171

申请日：2006-03-23

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  ANDERSON, William C.

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  ANDERSON, William C.

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/3853

Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encoding a plurality of instructions of a first length and a plurality of instructions of a second length. The method and system encode a header having at least one instruction length bit. The instruction bit distinguishes between instructions of the first length and instructions of the second length for an associated DSP to process in a mixed stream. The method and system distinguish between the instructions of the first length and the instructions of the second length according to the contents of the instruction length bits. The header further includes bits for distinguishing between instructions of varying lengths in an instruction packet.

Abstract translation: 用于在通信（例如，CDMA）系统中处理传输的技术。 该方法和系统编码和处理混合长度（例如，16位和32位）的指令以及包括混合长度指令的指令包。 这包括编码具有第二长度的第一长度和多个指令的多个指令。 该方法和系统对具有至少一个指令长度位的报头进行编码。 指令位区分第一长度的指令和第二长度的指令，以使相关的DSP在混合流中进行处理。 方法和系统根据指令长度位的内容区分第一长度的指令和第二长度的指令。 标题还包括用于区分指令包中不同长度的指令的位。