公开(公告)号：WO2012061417A1

公开(公告)日：2012-05-10

申请号：PCT/US2011/058824

申请日：2011-11-01

Applicant: QUALCOMM Incorporated ,  LIN, Jentsung Ken ,  INGLE, Ajay Anant ,  KUO, Eai-hsin A. ,  BASSETT, Paul Douglas

Inventor： LIN, Jentsung Ken ,  INGLE, Ajay Anant ,  KUO, Eai-hsin A. ,  BASSETT, Paul Douglas

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/30043 ,  G06F9/3857

Abstract: A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When at least one instruction cannot architecturally complete, delaying both instructions. When both instructions can architecturally complete and at least one is a write instruction, adjusting a write control of the memory to account for an evaluation delay. The evaluation delay can be sufficient to evaluate whether both instructions can architecturally complete. The evaluation delay can be input to the write control and not the read control of the memory. A precharge clock of the memory can be adjusted to account for the evaluation delay. Evaluating whether both instructions can architecturally complete can include determining whether data for each instruction is located in a cache, and whether the instructions are memory access instructions.

Abstract translation: 一种用于控制对存储器的系统访问的方法和装置，包括接收第一和第二指令，以及评估两种指令是否可以在架构上完成。 当至少一个指令不能在架构上完成时，延迟两个指令。 当两个指令都可以在架构上完成并且至少一个是写指令时，调整存储器的写入控制以考虑评估延迟。 评估延迟足以评估两种指令是否可以在架构上完成。 评估延迟可以输入到写入控制，而不是存储器的读取控制。 可以调整存储器的预充电时钟以考虑评估延迟。 评估两种指令是否可以在架构上完成可以包括确定每个指令的数据是否位于高速缓存中，以及指令是否是存储器访问指令。

公开(公告)号：WO2011088351A1

公开(公告)日：2011-07-21

申请号：PCT/US2011/021342

申请日：2011-01-14

Applicant: QUALCOMM INCORPORATED ,  INGLE, Ajay Anant ,  LIN, Jentsung ,  TOLEY, Rahul R.

Inventor： INGLE, Ajay Anant ,  LIN, Jentsung ,  TOLEY, Rahul R.

IPC: G06F13/16

CPC classification number: G06F13/1678

Abstract: A multi-stage multiplexing operation that includes combined selection and data alignment or data replication is disclosed. In a particular embodiment, a method includes performing a first stage of a multi-stage multiplexing operation. During the first stage, a first data source is selected from a first plurality of data sources. At least one of a first data alignment operation and a first data replication operation is also performed on first data from the selected first data source during the first stage.

Abstract translation: 公开了包括组合选择和数据对准或数据复制的多级复用操作。 在特定实施例中，一种方法包括执行多级复用操作的第一级。 在第一阶段期间，从第一多个数据源中选择第一数据源。 在第一阶段期间，还对来自所选择的第一数据源的第一数据执行第一数据对准操作和第一数据复制操作中的至少一个。

公开(公告)号：WO2009062077A1

公开(公告)日：2009-05-14

申请号：PCT/US2008/082857

申请日：2008-11-07

Applicant: QUALCOMM INCORPORATED ,  BASSETT, Paul ,  CODRESCU, Lucian ,  INGLE, Ajay Anant ,  PLONDKE, Erich

Inventor： BASSETT, Paul ,  CODRESCU, Lucian ,  INGLE, Ajay Anant ,  PLONDKE, Erich

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/1028 ,  Y02D10/13

Abstract: The disclosure includes a method and system of configuring a translation lookaside buffer (TLB). In an embodiment, the TLB includes a first portion and a second portion. The first portion or the second portion may be selectively disabled in response to a value of a TLB configuration indicator.

Abstract translation: 本公开包括配置翻译后备缓冲器（TLB）的方法和系统。 在一个实施例中，TLB包括第一部分和第二部分。 可以响应于TLB配置指示符的值来选择性地禁用第一部分或第二部分。

公开(公告)号：EP3033670B1

公开(公告)日：2019-11-06

申请号：EP14759362.8

申请日：2014-08-04

Applicant: Qualcomm Incorporated

Inventor： INGLE, Ajay Anant ,  HOFFMAN, Marc Murray ,  MATHEW, Deepak ,  ZENG, Mao

IPC: G06F9/30 ,  G06F9/38

公开(公告)号：EP3051412A1

公开(公告)日：2016-08-03

申请号：EP15190669.0

申请日：2012-08-24

Applicant: QUALCOMM Incorporated

Inventor： FRIDMAN, Jose ,  INGLE, Ajay Anant ,  MATHEW, Deepak ,  HOFFMAN, Marc, M. ,  LOPEZ, Michael, John

IPC: G06F9/30 ,  G06F15/80

CPC classification number: G06F15/8084 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109

Abstract: Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.

Abstract translation: 公开了向量处理器中的数据提取的系统和方法。 在特定实施例中，向量处理器中的数据提取方法包括将至少一个数据元素复制到置换网络的源寄存器。 该方法包括重新排序源寄存器的多个数据元素，用重新排序的数据元素填充置换网络的目的地寄存器，以及将重新排序的数据元素从目的地寄存器复制到存储器。

公开(公告)号：EP2542963B1

公开(公告)日：2016-02-24

申请号：EP11708631.4

申请日：2011-03-02

Applicant: Qualcomm Incorporated

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich James ,  INGLE, Ajay Anant ,  VENKUMAHANTI, Suresh K. ,  TABONY, Charles Joseph

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/30149

公开(公告)号：EP2974051A1

公开(公告)日：2016-01-20

申请号：EP14717009.6

申请日：2014-03-12

Applicant: Qualcomm Incorporated

Inventor： MATHEW, Deepak ,  INGLE, Ajay Anant ,  ZENG,Mao ,  HOFFMAN, Marc M.

IPC: H04B1/7093 ,  H04B1/7075 ,  H03H17/02

CPC classification number: H04L25/0212 ,  H04B1/70752 ,  H04B1/7093 ,  H04B2201/70707

Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

公开(公告)号：EP3326060A1

公开(公告)日：2018-05-30

申请号：EP16732213.0

申请日：2016-06-21

Applicant: Qualcomm Incorporated

Inventor： MAHURIN, Eric Wayne ,  INGLE, Ajay Anant

IPC: G06F9/30

Abstract: Systems and methods relate to a mixed-width single instruction multiple data (SIMD) instruction which has at least a source vector operand comprising data elements of a first bit-width and a destination vector operand comprising data elements of a second bit-width, wherein the second bit-width is either half of or twice the first bit-width. Correspondingly, one of the source or destination vector operands is expressed as a pair of registers, a first register and a second register. The other vector operand is expressed as a single register. Data elements of the first register correspond to even-numbered data elements of the other vector operand expressed as a single register, and data elements of the second register correspond to data elements of the other vector operand expressed as a single register.

公开(公告)号：EP2909713B1

公开(公告)日：2017-07-05

申请号：EP13780470.4

申请日：2013-10-09

Applicant: Qualcomm Incorporated

Inventor： INGLE, Ajay Anant ,  HOFFMAN, Marc M. ,  MATHEW, Deepak

IPC: G06F9/30

CPC classification number: G06F9/30141 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3012

公开(公告)号：EP2761434B1

公开(公告)日：2017-06-14

申请号：EP12783712.8

申请日：2012-09-30

Applicant: Qualcomm Incorporated

Inventor： ZENG, Mao ,  CODRESCU, Lucian ,  PLONDKE, Erich James ,  INGLE, Ajay Anant

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/30032 ,  G06F9/30043

Abstract: An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.

Abstract translation: 一条指令标识一个寄存器和一个存储器位置。 在处理器执行指令后，从存储器位置加载项目，并执行移位和插入操作以移位寄存器中的数据并将项目插入寄存器。