公开(公告)号：WO2015123301A1

公开(公告)日：2015-08-20

申请号：PCT/US2015/015421

申请日：2015-02-11

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Jae Sik ,  WE, Hong Bok ,  KIM, Dong Wook ,  GU, Shiqun

IPC: H01L23/498 ,  H01L25/10

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

Abstract translation: 一些新颖的特征涉及包括封装层，穿过封装层的通孔结构和衬垫的集成器件。 通孔结构包括通孔，其包括第一侧，第二侧和第三侧。 通孔结构还包括至少围绕通孔的第一侧和第三侧的阻挡层。 焊盘直接耦合到通孔结构的阻挡层。 在一些实现中，集成器件包括耦合到封装层的第一表面的第一介电层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的衬底。 在一些实施方案中，集成器件包括耦合到衬底的第一管芯，其中封装层封装第一管芯。 在一些实施方式中，通孔包括被配置为作为垫进行操作的部分。

公开(公告)号：EP3132469B1

公开(公告)日：2019-01-09

申请号：EP15718725.3

申请日：2015-04-10

Applicant: Qualcomm Incorporated

Inventor： WE, Hong Bok ,  KIM, Chin-Kwan ,  KIM, Dong Wook ,  LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48

公开(公告)号：EP3329512A1

公开(公告)日：2018-06-06

申请号：EP16751411.6

申请日：2016-07-28

Applicant: Qualcomm Incorporated

Inventor： WE, Hong Bok ,  LEE, Jae Sik ,  KIM, Dong Wook ,  GU, Shiqun

IPC: H01L21/60 ,  H01L23/538 ,  H01L23/13 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L21/52 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package-on-package (POP) structure is disclosed. The POP structure includes a first die, a second die, and a photo-imaged dielectric (PID) layer. The PID layer is disposed between the first die and the second die. The POP structure also includes a first conductive path from the first die through the PID layer to the second die. The first conductive path extends directly through a first area of the PID layer directly between the first die and the second die. The POP structure further includes a second conductive path from the first die through the PID layer to the second die. A particular portion of the second conductive path is perpendicular to the first conductive path and extends through a second area of the PID layer not directly between the first die and the second die.

公开(公告)号：EP3198641A1

公开(公告)日：2017-08-02

申请号：EP15775578.6

申请日：2015-09-25

Applicant: Qualcomm Incorporated

Inventor： KIM, Dong Wook ,  LEE, Jae Sik ,  WE, Hong Bok ,  SONG, Young Kyu ,  KIM, Chin-Kwan ,  HWANG, Kyu-Pyung ,  GU, Shiqun

IPC: H01L23/538 ,  H01L21/60

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: A semiconductor package according to some examples of the disclosure may include a base (110) with a first redistribution layer (150) on one side, first (120) and second (130) side-by-side die attached to the base on an opposite side from the first redistribution layer, an interposer (140) attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias (180,181) extending from the first and second die to a second redistribution layer (170) on a surface of the package opposite the first redistribution layer, and a plurality of package vias (182) extending through the package between the first and second redistribution layers.

Abstract translation: 根据本公开的一些示例的半导体封装件可以包括基底，在一侧具有第一再分布层，在与第一再分布层相对的一侧上附着到基底的第一和第二并排管芯，附着到有源侧的插入物 提供第一和第二管芯之间的互连;多个管芯通孔，从第一和第二管芯延伸到与第一再分配层相对的封装表面上的第二再分配层;以及多个 在第一和第二重新分布层之间延伸穿过封装的封装过孔。

公开(公告)号：EP4546409A2

公开(公告)日：2025-04-30

申请号：EP25163073.7

申请日：2016-05-24

Applicant: QUALCOMM Incorporated

Inventor： LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  WE, Hong Bok

IPC: H01L23/00

Abstract: A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

公开(公告)号：EP3216055A1

公开(公告)日：2017-09-13

申请号：EP15794782.1

申请日：2015-11-05

Applicant: Qualcomm Incorporated

Inventor： LEE, Jae Sik ,  WE, Hong Bok ,  KIM, Dong Wook ,  GU, Shiqun

IPC: H01L23/538

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.

Abstract translation: 一些新颖的特征涉及包括封装部分和再分布部分的集成器件封装。 封装部分包括第一裸片，耦合到第一裸片的第一组通孔，第二裸片，耦合到第二裸片的第二组通孔，桥和封装层。 桥被配置为在第一管芯和第二管芯之间提供电路径。 桥通过第一组通孔耦合到第一管芯。 该桥通过第二组通孔进一步耦合到第二管芯。 封装层至少部分封装第一管芯，第二管芯，桥，第一组通孔和第二组通孔。 再分布部分连接到封装部分。 再分布部分包括一组再分布互连和至少一个介电层。

公开(公告)号：EP3338303A1

公开(公告)日：2018-06-27

申请号：EP16730956.6

申请日：2016-06-03

Applicant: Qualcomm Incorporated

Inventor： GU, Shiqun ,  WE, Hong Bok ,  LEE, Jae Sik ,  KIM, Dong Wook

IPC: H01L23/538

CPC classification number: H01L23/5385 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated device package includes a first die, a second die, an encapsulation portion coupled to the first die and the second die, and a redistribution portion coupled to the encapsulation portion. The encapsulation portion includes an encapsulation layer, a bridge, and a first via. The bridge is at least partially embedded in the encapsulation layer. The bridge is configured to provide a first electrical path for a first signal between the first die and the second die. The first via is in the encapsulation layer. The first via is coupled to the bridge. The first via and the bridge are configured to provide a second electrical path for a second signal to the first die. The redistribution portion includes at least one dielectric layer, and at least one interconnect, in the dielectric layer, coupled to the first via.

公开(公告)号：EP3140861A1

公开(公告)日：2017-03-15

申请号：EP15723397.4

申请日：2015-05-05

Applicant: Qualcomm Incorporated

Inventor： WE, Hong Bok ,  KIM, Dong Wook ,  LEE, Jae Sik ,  GU, Shiqun ,  RADOJCIC, Ratibor

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/49827 ,  H01L21/31127 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/20648 ,  H01L2924/3511 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09563 ,  H01L2924/014 ,  H01L2224/81

Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

Abstract translation: 提供了具有增加的宽度的衬底块。 衬底块包括两个衬底条，并且衬底条各自包括衬底和穿过衬底的多个填充的通孔。 衬底块可用于制造封装衬底，并且这些封装衬底可以并入PoP结构中。 封装衬底包括具有多个垂直互连的载体和耦合到垂直互连的条。

公开(公告)号：EP3140860A1

公开(公告)日：2017-03-15

申请号：EP15719392.1

申请日：2015-04-17

Applicant: Qualcomm Incorporated

Inventor： GU, Shiqun ,  RADOJCIC, Ratibor ,  KIM, Dong Wook ,  LEE, Jae Sik

IPC: H01L23/498 ,  H01L21/48 ,  H05K3/46 ,  H01L21/56 ,  H01L23/14 ,  H01L25/065 ,  H01L25/10 ,  H01L21/60

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/171 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/18161 ,  H05K3/4688 ,  H01L2924/014

Abstract: An integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (206) (e.g., first wafer level die), and a second die (208) (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer (203), a first set of interconnects (280) located in the first inorganic dielectric layer, a second dielectric layer (202) different from the first inorganic dielectric layer, and a set of redistribution metal layers (230,240,250,260) in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects (280).

Abstract translation: 一些新颖的特征涉及在集成的装置（例如，集成的封装）那样包括用于集成装置，第一对（例如，第一晶片级模）的基部，和一个第二即（E. G.，第二晶片级模）。 基座部分包括第一无机介电层，第一组位于所述第一无机介电层中的互连，第二介电层从所述第一无机介电层不同，并且所述第二介电层中的一组再分布金属层。 第一个是连接到所述底座部分的第一表面上。 第二，其耦合到所述底座部分的第一表面，第二个是电通过所述第一组互连耦合到所述第一。

公开(公告)号：EP4439634A3

公开(公告)日：2025-01-15

申请号：EP24194383.6

申请日：2016-07-28

Applicant: QUALCOMM Incorporated

Inventor： WE, Hong Bok ,  LEE, Jae Sik ,  KIM, Dong Wook ,  GU, Shiqun

IPC: H01L21/60 ,  H01L23/538 ,  H01L23/13 ,  H01L23/498 ,  H01L21/56

Abstract: A package-on-package (POP) structure is disclosed. The POP structure includes a first die, a second die, and a photo-imaged dielectric (PID) layer. The PID layer is disposed between the first die and the second die. The POP structure also includes a first conductive path from the first die through the PID layer to the second die. The first conductive path extends directly through a first area of the PID layer directly between the first die and the second die. The POP structure further includes a second conductive path from the first die through the PID layer to the second die. A particular portion of the second conductive path is perpendicular to the first conductive path and extends through a second area of the PID layer not directly between the first die and the second die.