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    CIRCUITS AND METHODS PROVIDING THREE-LEVEL SIGNALS AT A SYNCHRONOUS BUCK CONVERTER
    21.
    发明公开
    CIRCUITS AND METHODS PROVIDING THREE-LEVEL SIGNALS AT A SYNCHRONOUS BUCK CONVERTER 审中-公开
    在同步降压转换器上提供三电平信号的电路和方法

    公开(公告)号：EP3210288A1

    公开(公告)日：2017-08-30

    申请号：EP15781795.8

    申请日：2015-09-24

    Applicant: Qualcomm Incorporated

    Inventor： ZHANG, Chuang ,  DOYLE, James, Thomas ,  MAHMOUDI, Farsheed ,  SHAYAN ARANI, Amirali

    IPC: H02M1/12 ,  H02M3/07 ,  H02M7/483 ,  H03H7/01

    CPC classification number: H02M3/158 ,  H02M1/14 ,  H02M7/483 ,  H02M2003/072

    Abstract: A circuit including: a three-level buck converter having: a plurality of input switches and an inductor configured to receive a voltage from the plurality of input switches, the plurality of input switches coupled with a first capacitor and configured to charge and discharge the first capacitor; a second capacitor at an output of the buck converter; and a switched capacitor at an input node of the inductor, wherein the switched capacitor is smaller than either the first capacitor or the second capacitor.

    Abstract translation: 一种电路，包括：三电平降压转换器，具有：多个输入开关和电感器，所述多个输入开关和电感器被配置为从所述多个输入开关接收电压，所述多个输入开关与第一电容器耦合并且被配置为对所述第一电容器 电容器; 在降压转换器的输出处的第二电容器; 以及在所述电感器的输入节点处的开关电容器，其中所述开关电容器小于所述第一电容器或所述第二电容器。

    SINGLE LDO FOR MULTPLE VOLTAGE DOMAINS
    24.
    发明公开
    SINGLE LDO FOR MULTPLE VOLTAGE DOMAINS 审中-公开

    公开(公告)号：EP3338154A1

    公开(公告)日：2018-06-27

    申请号：EP16754069.9

    申请日：2016-08-09

    Applicant: Qualcomm Incorporated

    Inventor： MAHMOUDI, Farsheed ,  SHAHROKHINIA, Sassan ,  DOYLE, James Thomas

    IPC: G05F1/575

    CPC classification number: G05F1/575

    Abstract: Low dropout (LDO) regulators are described herein for providing regulated voltages for multiple voltage domains. In one embodiment, a voltage regulator comprises a plurality of pass transistors, each of the plurality of pass transistors being coupled between an input supply rail and a respective one of a plurality of regulator outputs. The voltage regulator also comprises a plurality of averaging resistors configured to average a plurality of feedback voltages to generate an average feedback voltage, wherein each of the plurality of feedback voltages provides voltage feedback for a respective one of the plurality of regulator outputs. The voltage regular further comprises an amplifier having a first input coupled to the average feedback voltage, and a second input coupled to a reference voltage, wherein the amplifier is configured to drive the plurality of pass transistors in a direction that reduces a difference between the reference voltage and the average feedback voltage.

    CIRCUITS AND METHODS PROVIDING DEAD TIME ADJUSTMENT AT A SYNCHRONOUS BUCK CONVERTER
    25.
    发明公开
    CIRCUITS AND METHODS PROVIDING DEAD TIME ADJUSTMENT AT A SYNCHRONOUS BUCK CONVERTER 审中-公开
    在同步降压转换器上提供死区时间调整的电路和方法

    公开(公告)号：EP3210291A1

    公开(公告)日：2017-08-30

    申请号：EP15791142.1

    申请日：2015-10-22

    Applicant: Qualcomm Incorporated

    Inventor： DOYLE, James Thomas ,  MAHMOUDI, Farsheed ,  ZHANG, Chuang ,  FU, Zhengming ,  SHAHROKHINIA, Sassan

    IPC: H02M1/38 ,  H02M3/157 ,  H02M1/00

    CPC classification number: H02M3/158 ,  H02M1/38 ,  H02M3/157 ,  H02M2001/0012 ,  H02M2001/0048 ,  Y02B70/1491

    Abstract: An apparatus and method are disclosed for efficiently using power at a voltage regulator, such as a synchronous buck converter. The synchronous buck converter includes a first switch and a second switch operated by a first control signal and a second control signal, respectively, where the first and second control signals have a corresponding phase difference. A logic circuit measures a duty cycle of an input pulse width modulated (PWM) signal against iterative changes of the phase difference between the first control signal and the second control signal. The logic circuit selects a phase difference corresponding to a minimum value of the PWM signal, thereby optimizing dead time at the synchronous buck converter. The logic circuit may include a Digital Pulse Width Modulator.

    Abstract translation: 公开了一种用于在诸如同步降压转换器之类的电压调节器上有效使用功率的设备和方法。 同步降压转换器包括分别由第一控制信号和第二控制信号操作的第一开关和第二开关，其中第一和第二控制信号具有对应的相位差。 逻辑电路针对第一控制信号和第二控制信号之间的相位差的迭代变化来测量输入脉宽调制（PWM）信号的占空比。 逻辑电路选择对应于PWM信号的最小值的相位差，由此优化同步降压转换器的死区时间。 逻辑电路可以包括数字脉宽调制器。

    CIRCUITS AND METHODS PROVIDING HIGH EFFICIENCY OVER A WIDE RANGE OF LOAD VALUES
    27.
    发明公开
    CIRCUITS AND METHODS PROVIDING HIGH EFFICIENCY OVER A WIDE RANGE OF LOAD VALUES 审中-公开
    电路和方法在广泛的负载值范围内提供高效率

    公开(公告)号：EP3210287A1

    公开(公告)日：2017-08-30

    申请号：EP15775568.7

    申请日：2015-09-24

    Applicant: Qualcomm Incorporated

    Inventor： MAHMOUDI, Farsheed ,  DOYLE, James Thomas ,  ZHANG, Chuang ,  FU, Zhengming

    IPC: H02M1/088 ,  H02M3/158 ,  H02M3/157 ,  H02M1/00

    CPC classification number: H02M3/1584 ,  G06F1/3296 ,  H02M1/088 ,  H02M3/157 ,  H02M2001/0048 ,  H02M2001/0054 ,  Y02B70/1491

    Abstract: An apparatus and method are disclosed for providing efficient operation in a feedback loop having a synchronous buck converter. The synchronous buck converter includes a plurality of individually selectable phases, where each of the phases has a plurality of individually selectable and parallel switching legs. The circuit stores information that associates multiple different load values with respective configuration settings that each define a number of phases and a number of switching legs. As the load changes, the circuit measures the load and selects an appropriate configuration setting. The circuit applies the selected configuration setting to operate the number of phases and a number of parallel switching legs in the buck converter.

    Abstract translation: 公开了一种用于在具有同步降压转换器的反馈回路中提供有效操作的设备和方法。 同步降压转换器包括多个可单独选择的相，其中每个相具有多个可单独选择和并联的开关支路。 该电路存储将多个不同负载值与各个配置设置相关联的信息，每个配置设置定义多个阶段和多个切换支路。 随着负载的变化，电路会测量负载并选择适当的配置设置。 该电路应用选定的配置设置来操作降压转换器中的相数和并联开关支路的数量。

    SUBSTRATE-LESS DISCRETE COUPLED INDUCTOR STRUCTURE
    28.
    发明公开
    SUBSTRATE-LESS DISCRETE COUPLED INDUCTOR STRUCTURE 审中-公开
    SUBSTRATLOSE，DISKRETE，GEKOPPELTE INDUKTORSTRUKTUR

    公开(公告)号：EP2954543A1

    公开(公告)日：2015-12-16

    申请号：EP14706170.9

    申请日：2014-01-31

    Applicant: Qualcomm Incorporated

    Inventor： DOYLE, James Thomas ,  MAHMOUDI, Farsheed ,  ARANI, AmiraliShayan

    IPC: H01F17/00 ,  H01L23/64 ,  H01L49/02

    CPC classification number: H01L23/49822 ,  H01F17/0006 ,  H01L23/645 ,  H01L25/105 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15313 ,  H01L2924/15331 ,  H01L2924/19106 ,  Y10T29/4902 ,  H01L2924/00

    Abstract: Some novel features pertain to an inductor structure that includes a first inductor winding, a second inductor winding and a filler. The first inductor winding includes an electrically conductive material. The second inductor winding includes an electrically conductive material. The filler is laterally located between the first inductor winding and the second inductor winding. The filler is configured to provide structural coupling of the first and second inductor windings. In some implementations, the first inductor winding is laterally co-planar to the second inductor winding. In some implementations, the first inductor winding has a first spiral shape and the second inductor winding has a second spiral shape. In some implementations, the first inductor winding and the second inductor winding have an elongated circular shape. In some implementations, the filler is an epoxy.

    Abstract translation: 一些新颖的特征涉及一种电感器结构，其包括第一电感器绕组，第二电感器绕组和填充器。 第一电感线圈包括导电材料。 第二电感线圈包括导电材料。 填料侧向位于第一电感器绕组和第二电感器绕组之间。 填充物被配置为提供第一和第二电感器绕组的结构耦合。 在一些实施方案中，第一电感器绕组与第二电感器绕组横向共面。 在一些实施方案中，第一电感器绕组具有第一螺旋形状，并且第二电感器绕组具有第二螺旋形状。 在一些实施方案中，第一电感器绕组和第二电感器绕组具有细长的圆形形状。 在一些实施方案中，填料是环氧树脂。

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