公开(公告)号：WO2008113007A1

公开(公告)日：2008-09-18

申请号：PCT/US2008/057064

申请日：2008-03-14

Applicant: QUALCOMM Incorporated ,  SARTORIUS, Thomas Andrew ,  STEMPEL, Brian Michael ,  SMITH, Rodney Wayne

Inventor： SARTORIUS, Thomas Andrew ,  STEMPEL, Brian Michael ,  SMITH, Rodney Wayne

IPC: G06F9/318 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30196 ,  G06F9/30047 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/382

Abstract: An instruction preload instruction executed in a first processor instruction set operating mode is operative to correctly preload instructions in a different, second instruction set. The instructions are pre-decoded according to the second instruction set encoding in response to an instruction set preload indicator (ISPI). In various embodiments, the ISPI may be set prior to executing the preload instruction, or may comprise part of the preload instruction or the preload target address.

Abstract translation: 在第一处理器指令集操作模式中执行的指令预加载指令可操作以在不同的第二指令集中正确地预加载指令。 根据指令集预加载指示符（ISPI），根据第二指令集编码对指令进行预解码。 在各种实施例中，可以在执行预加载指令之前设置ISPI，或者可以包括预加载指令或预加载目标地址的一部分。

公开(公告)号：WO2008098140A1

公开(公告)日：2008-08-14

申请号：PCT/US2008/053338

申请日：2008-02-07

Applicant: QUALCOMM Incorporated ,  KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

Inventor： KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

IPC: G06F12/04

CPC classification number: G06F12/04 ,  G06F12/1027 ,  G06F2212/655 ,  Y02D10/13

Abstract: Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.

Abstract translation: 通过识别导致存储器中的不同页面之间的边界交叉的地址以及链接与两个存储器页面相关联的地址转换信息来改进处理器内的地址转换性能。 根据处理器的一个实施例，处理器包括被配置为识别对跨越第一和第二存储器页之间的页边界的存储区的访问的电路。 电路还被配置为链接与第一和第二存储器页相关联的地址转换信息。 因此，响应于后续访问相同的存储器区域，可以基于单个地址转换来检索与第一和第二存储器页面相关联的地址转换信息。

公开(公告)号：WO2008055045A1

公开(公告)日：2008-05-08

申请号：PCT/US2007/082538

申请日：2007-10-25

Applicant: QUALCOMM INCORPORATED ,  STEMPEL, Brian Michael ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

Inventor： STEMPEL, Brian Michael ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

IPC: G06F9/38

CPC classification number: G06F9/3848 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3861

Abstract: A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline stages. The method verifies that a branch instruction has been identified. The method further receives branch history information during a first pipeline stage and loads the branch history information into a first register, wherein the first register. The method further loads the branch history information into the second register during the second pipeline stage.

Abstract translation: 公开了处理分支历史信息的方法。 该方法从指令高速缓存中检索分支指令，并在多个流水线级中执行分支指令。 该方法验证分支指令已被识别。 该方法还在第一流水线阶段期间接收分支历史信息，并将分支历史信息加载到第一寄存器中，其中第一寄存器。 该方法在第二流水线阶段期间进一步将分支历史信息加载到第二寄存器中。

公开(公告)号：WO2007143508A2

公开(公告)日：2007-12-13

申请号：PCT/US2007/070111

申请日：2007-05-31

Applicant: QUALCOMM Incorporated ,  SMITH, Rodney Wayne ,  DIEFFENDERFER, James Norris ,  STEMPEL, Brian Michael ,  SARTORIUS, Thomas Andrew

Inventor： SMITH, Rodney Wayne ,  DIEFFENDERFER, James Norris ,  STEMPEL, Brian Michael ,  SARTORIUS, Thomas Andrew

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3836 ,  G06F9/3844

Abstract: A sliding-window, block-based branch target address cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the branch target address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.

Abstract translation: 滑动窗口，基于块的分支目标地址高速缓存（BTAC）包括多个条目，每个条目与包含已被评估的至少一个分支指令的指令块相关联，并且具有与该地址相关联的标签 第一个指令在块中。 这些块各自对应于从存储器获取的一组指令，例如I缓存。 在两个或更多个取出组中包含分支指令的情况下，还包括在与BTAC条目相关联的两个或多个指令块中。 滑动窗口，基于块的BTAC允许存储落在相同指令块中的两个或更多个采取的分支指令的分支目标地址（BTA），而不需要在每个BTAC条目中提供多个BTA存储空间，通过存储BTAC条目 与不同的指令块相关联，每个指令块包含至少一个采取的分支指令。

公开(公告)号：WO2007085009A1

公开(公告)日：2007-07-26

申请号：PCT/US2007/060813

申请日：2007-01-22

Applicant: QUALCOMM INCORPORATED ,  KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

Inventor： KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

IPC: G06F9/38

CPC classification number: G06F9/3861 ,  G06F12/1027

Abstract: A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a "hit" in the TLB upon its next access.

Abstract translation: 具有多级流水线的处理器包括TLB和TLB控制器。 响应于TLB未命中信号，TLB控制器启动TLB重新加载，从存储器或更高级TLB请求地址转换信息，并将该信息放入TLB。 处理器刷新具有缺失的虚拟地址的指令，并且重新指示该指令，从而导致在TLB接入点上方的管线的初始阶段重新插入该指令。 TLB重新启动的启动以及指令的刷新/刷新基本上并行执行，并且不会立即停止管道。 重写指令在TLB接入点上方的管道中保持一段时间，直到TLB重新加载完成，这样，重写指令在下一次访问时就会在TLB中产生一个“命中”。

公开(公告)号：WO2007002803A2

公开(公告)日：2007-01-04

申请号：PCT/US2006/025301

申请日：2006-06-27

Applicant: QUALCOMM Incorporated ,  KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

Inventor： KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

IPC: G06F12/10

CPC classification number: G06F9/3802 ,  G06F12/1027 ,  G06F2212/655 ,  Y02D10/13

Abstract: A processor includes a memory configured to store data in a plurality of pages, a TLB, and a TLB controller. The TLB is configured to search, when accessed by an instruction having a virtual address, for address translation information that allows the virtual address to be translated into a physical address of one of the plurality of pages, and to provide the address translation information if the address translation information is found within the TLB. The TLB controller is configured to determine whether a current instruction and a subsequent instruction seek access to a same page within the plurality of pages, and if so, to prevent TLB access by the subsequent instruction, and to utilize the results of the TLB access of a previous instruction for the current instruction.

Abstract translation: 处理器包括被配置为将数据存储在多个页面中的存储器，TLB和TLB控制器。 TLB被配置为当被具有虚拟地址的指令访问时搜索允许虚拟地址被翻译成多个页面之一的物理地址的地址翻译信息，并且如果 地址转换信息在TLB中找到。 TLB控制器被配置为确定当前指令和后续指令是否寻求访问多个页面内的同一页面，并且如果是，则阻止后续指令对TLB访问，并利用TLB访问的结果 当前指令的先前指令。

公开(公告)号：WO2006086713A3

公开(公告)日：2006-08-17

申请号：PCT/US2006/004892

申请日：2006-02-10

Applicant: QUALCOMM INCORPORATED ,  MCILVAINE, Michael Scott ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

Inventor： MCILVAINE, Michael Scott ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

IPC: G06F9/38 ,  G06F9/318

Abstract: Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The emissary instruction evaluates the condition and reports the condition evaluation back to the base instruction. Based on the condition evaluation, the base instruction is either launched into the pipeline for execution, or it is discarded (or a NOP, or null instruction, substituted for it). In either case, the dependencies of following instructions may be resolved.

公开(公告)号：WO2018118719A1

公开(公告)日：2018-06-28

申请号：PCT/US2017/066879

申请日：2017-12-15

Applicant: QUALCOMM INCORPORATED

Inventor： SARTORIUS, Thomas Andrew ,  DIEFFENDERFER, James Norris ,  SPEIER, Thomas Philip ,  MCILVAINE, Michael Scott ,  MORROW, Michael William

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F16/24558 ,  G06F2212/6024 ,  G06F2212/6026

Abstract: Systems and methods are directed to prefetch mechanisms involving non-equal magnitude stride values. A non-equal magnitude functional relationship between successive stride values, may be detected, wherein the stride values are based on distances between target addresses of successive load instructions. At least a next stride value for prefetching data, may be determined, wherein the next stride value is based on the non-equal magnitude functional relationship and a previous stride value. Data prefetch may be from at least one prefetch address calculated based on the next stride value and a previous target address. The non-equal magnitude functional relationship may include a logarithmic relationship corresponding to a binary search algorithm.

公开(公告)号：WO2017053109A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/051241

申请日：2016-09-12

Applicant: QUALCOMM INCORPORATED

Inventor： CAIN III, Harold Wade ,  HOWER, Derek Robert ,  DAMODARAN, Raguram ,  SARTORIUS, Thomas Andrew

IPC: G06F12/0842 ,  G06F12/0895 ,  G06F12/0815 ,  G06F12/0888

CPC classification number: G06F12/121 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0888 ,  G06F12/0895 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/621 ,  Y02D10/13

Abstract: A cache fill line is received, including an index, a thread identifier, and cache fill line data. The cache is probed, using the index and a different thread identifier, for a potential duplicate cache line. The potential duplicate cache line includes cache line data and the different thread identifier. Upon the cache fill line data matching the cache line data, duplication is identified. The potential duplicate cache line is set as a shared resident cache line, and the thread share permission tag is set to a permission state.

Abstract translation: 接收缓存填充行，包括索引，线程标识符和缓存填充行数据。 使用索引和不同的线程标识符探测高速缓存，用于潜在的重复高速缓存行。 潜在的重复缓存行包括高速缓存行数据和不同的线程标识符。 当缓存填充线数据与高速缓存线数据匹配时，识别出重复。 将潜在的重复缓存行设置为共享驻留高速缓存行，并将线程共享权限标记设置为权限状态。

公开(公告)号：WO2016186747A1

公开(公告)日：2016-11-24

申请号：PCT/US2016/026664

申请日：2016-04-08

Applicant: QUALCOMM INCORPORATED

Inventor： PELLERIN, III, Henry Arthur ,  SPEIER, Thomas Philip ,  SARTORIUS, Thomas Andrew ,  MORROW, Michael William ,  DIEFFENDERFER, James Norris ,  DOCKSER, Kenneth Alan ,  MCILVAINE, Michael Scott

IPC: G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/401 ,  G06F2212/6032 ,  G06F2212/621

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract translation: 存储器结构使用索引标签压缩结构压缩存储器标签的一部分。 存储器标签的一组较高位可以存储在索引标签压缩结构中，其中较高位的集合由索引值标识。 标签阵列存储存储器标签的一组较低位，以及标识在存储标签的较高位的集合的标签压缩结构中的条目的索引值。 存储器标签可以包括存储在数据阵列中的数据元素的存储器地址的至少一部分。