公开(公告)号：US09219032B2

公开(公告)日：2015-12-22

申请号：US13790625

申请日：2013-03-08

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Shiqun Gu

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13024

Abstract: A semiconductor wafer has an integrated through substrate via created from a backside of the semiconductor wafer. The semiconductor wafer includes a semiconductor substrate and a shallow trench isolation (STI) layer pad on a surface of the semiconductor substrate. The semiconductor wafer also includes an inter-layer dielectric (ILD) layer formed on a contact etch stop layer, separating the ILD layer from the STI layer pad on the surface of the semiconductor substrate. The semiconductor wafer further includes a through substrate via that extends through the STI layer pad and the semiconductor substrate to couple with at least one contact within the ILD layer. The through substrate via includes a conductive filler material and a sidewall isolation liner layer. The sidewall isolation liner layer has a portion that possibly extends into, but not through, the STI layer pad.

Abstract translation: 半导体晶片具有从半导体晶片的背面形成的集成通孔基板通孔。 半导体晶片包括在半导体衬底的表面上的半导体衬底和浅沟槽隔离（STI）层焊盘。 半导体晶片还包括形成在接触蚀刻停止层上的层间介电层（ILD）层，将ILD层与半导体衬底的表面上的STI层焊盘分离。 半导体晶片还包括穿过STI层焊盘和半导体衬底延伸穿过衬底通孔，以与ILD层内的至少一个触点耦合。 贯通基板通孔包括导电填充材料和侧壁隔离衬层。 侧壁隔离衬垫层具有可能延伸到但不穿过STI层衬垫的部分。

公开(公告)号：US08975729B2

公开(公告)日：2015-03-10

申请号：US13724038

申请日：2012-12-21

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Shiqun Gu

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer has an integrated through substrate via (TSV). The semiconductor wafer includes a substrate. A dielectric layer may be formed on a first side of the substrate. A through substrate via may extend through the dielectric layer and the substrate. The through substrate via may include a conductive material and an isolation layer. The isolation layer may at least partially surround the conductive material. The isolation layer may have a tapered portion.

Abstract translation: 半导体晶片具有集成的通过基板通孔（TSV）。 半导体晶片包括基板。 电介质层可以形成在衬底的第一侧上。 穿通基板通孔可以延伸通过介电层和基板。 贯通基板通孔可以包括导电材料和隔离层。 隔离层可以至少部分地围绕导电材料。 隔离层可以具有锥形部分。

公开(公告)号：US20140327105A1

公开(公告)日：2014-11-06

申请号：US13887723

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Vidhya Ramachandran ,  Brian M. Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L29/66 ,  H01L23/498 ,  H01L29/861

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。

公开(公告)号：US20140225208A1

公开(公告)日：2014-08-14

申请号：US13777475

申请日：2013-02-26

Applicant: QUALCOMM INCORPORATED

Inventor： Shiqun Gu ,  Ron Zhang ,  Vidhya Ramachandran ,  Dong Wook Kim

IPC: H01L43/02

CPC classification number: H01L43/12 ,  H01L23/3121 ,  H01L23/552 ,  H01L23/645 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/1435 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

Abstract translation: 一些实施方案提供了包括包括几个MRAM单元的磁阻随机存取存储器（MRAM）单元阵列的管芯。 芯片还包括位于MRAM单元阵列上方的第一铁磁层，位于MRAM单元阵列下方的第二铁磁层和位于至少一个MRAM单元周围的几个通孔。 通孔包括铁磁材料。 在一些实施方案中，第一铁磁层，第二铁磁层和几个通孔限定用于MRAM单元阵列的磁屏蔽。 MRAM单元可以包括磁性隧道结（MTJ）。 在一些实施方案中，几个通孔至少穿过管芯的金属层和电介质层。 在一些实施方案中，通孔通过衬底通孔。 在一些实施方案中，铁磁材料具有高磁导率和高B饱和度。