公开(公告)号：US20080205563A1

公开(公告)日：2008-08-28

申请号：US12028490

申请日：2008-02-08

Applicant: Richard D. Simpson ,  Nimal C. Warke

Inventor： Richard D. Simpson ,  Nimal C. Warke

IPC: H04B1/10

CPC classification number: H03H17/0261 ,  H04L25/03057 ,  H04L2025/03636

Abstract: The invention provides a particular construction for digital filters in which, instead of multiplying various ones of the digital samples by weights and adding the results together, one or more of the digital samples is inspected by a ranging unit, which then instructs an incrementing unit to increment, decrement or leave alone one of the samples to provide the result. In order to achieve very high data rates, the incremented and decremented values can be pre-prepared whilst the ranging unit makes its decision, and then a multiplexer responsive to the output of the ranging unit is used to select the appropriate one of the pre-prepared values.

Abstract translation: 本发明提供了一种用于数字滤波器的特定结构，其中，代替通过权重将各种数字样本相乘并将结果相加在一起，一个或多个数字样本由测距单元检查，测距单元然后指示增量单元 增加，减量或单独留下一个样品来提供结果。 为了实现非常高的数据速率，可以在测距单元进行判定的同时预先准备递增和递减的值，然后使用响应于测距单元的输出的多路复用器来选择预定义的适当的一个， 准备的价值观。

公开(公告)号：US20080192640A1

公开(公告)日：2008-08-14

申请号：US12028479

申请日：2008-02-08

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: G01R31/08

CPC classification number: H04L1/241 ,  H04L2025/03477 ,  H04L2025/0349

Abstract: A loopback circuit connecting the output of a receiver section to a transmitter section of a transceiver circuit has two or more loopback channels. In this way, the data rate is reduced, reducing the signal loss that occurs even over such short distances at very high data rates.

Abstract translation: 将接收机部分的输出连接到收发器电路的发射机部分的环回电路具有两个或多个环回信道。 以这种方式，数据速率降低，即使在非常高的数据速率下在这么短的距离上也能减少信号损失。

公开(公告)号：US06747504B2

公开(公告)日：2004-06-08

申请号：US10223282

申请日：2002-08-19

Applicant: Richard D. Simpson ,  Jonathan P. Milton ,  Simon D. Forey

Inventor： Richard D. Simpson ,  Jonathan P. Milton ,  Simon D. Forey

IPC: H03K1728

CPC classification number: H03K4/94 ,  H03K5/13 ,  H03K17/164 ,  H03K19/00361

Abstract: A control slew rate output driver has a plurality of component drivers that are switched on in turn to provide an edge on the output. A control circuit provides a series of respective control signals component drivers, which are correspondingly switched on in turn. The control circuit takes a signal, preferably a data signal, and supplies it in parallel to a plurality of delay buffers, which delay the data signal by different amounts to produce the control signals for the component drivers. The delay buffers are voltage controlled and the control voltage for each is provided by a respective tap of a voltage divider. The current passes through the voltage divider can be changed to change the control voltages and, hence, the overall rise or fall time provided by the output driver.

Abstract translation: 控制转换速率输出驱动器具有多个组件驱动器，其依次接通以在输出端提供边缘。 控制电路提供一系列相应的控制信号分量驱动器，其相应地依次接通。 控制电路采取信号，优选地是数据信号，并且将其并行地提供给多个延迟缓冲器，这些延迟缓冲器将数据信号延迟不同的量，以产生用于部件驱动器的控制信号。 延迟缓冲器是电压控制的，并且每个的控制电压由分压器的相应抽头提供。 可以改变通过分压器的电流来改变控制电压，从而改变由输出驱动器提供的整体上升或下降时间。

公开(公告)号：US6154824A

公开(公告)日：2000-11-28

申请号：US474866

申请日：1995-06-07

Applicant: Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

Inventor： Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

IPC: G06F3/14 ,  G09G1/16 ,  G09G5/00 ,  G09G5/06 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G06F12/00

CPC classification number: G06F3/1438 ,  G06F3/14 ,  G09G5/06 ,  G09G5/363 ,  G09G5/39 ,  G09G5/395 ,  G09G2360/126 ,  G09G5/001

Abstract: A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.

Abstract translation: 一种用于第一和第二数字计算机的多功能存取电路，每个数字计算机具有用于提供地址的地址总线和用于提供数据的数据总线。 访问电路具有地址解码器，其具有用于来自第一计算机的地址总线的输入，以及地址转换器电路，其具有用于由第一计算机的地址总线提供的地址的地址输入，并将翻译的地址输出到第二计算机的地址总线 。 地址转换器电路还具有可由地址解码器和数据输入端选择的寄存器，用来从第一台计算机的数据总线的数据对所选择的寄存器进行编程。 在访问电路中还有一个端口电路，具有由地址解码器控制的寄存器，用于从第一计算机的数据总线输入地址信息，并在第二计算机的地址总线上断言地址信息。 此外，模式控制电路连接到地址解码器并连接到数据总线以对模式控制电路进行编程，以选择性地建立地址转换器电路和端口电路的操作。 还描述了其他访问电路，设备，系统和方法。

公开(公告)号：US5696924A

公开(公告)日：1997-12-09

申请号：US487750

申请日：1995-06-07

Applicant: Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

Inventor： Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

IPC: G06F3/14 ,  G09G1/16 ,  G09G5/00 ,  G09G5/06 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G06F12/10

CPC classification number: G06F3/1438 ,  G06F3/14 ,  G09G5/06 ,  G09G5/363 ,  G09G5/39 ,  G09G5/395 ,  G09G2360/126 ,  G09G5/001

Abstract: A memory access system for use with a graphics processor having an address bus, a data bus and a set of control lines. An address translator circuit connected to the address bus of the graphics processor supplies a translated address to a memory upon receipt of an address from the graphics processor. A logic circuit responds to a write signal to automatically increment the translated address and responds to a control signal to return to the translated address. Control circuitry connected to the logic circuit responds to a read signal to supply the control signal to the logic circuit.

Abstract translation: 一种与具有地址总线，数据总线和一组控制线的图形处理器一起使用的存储器存取系统。 连接到图形处理器的地址总线的地址转换器电路在从图形处理器接收到地址时将翻译的地址提供给存储器。 一个逻辑电路响应一个写入信号，自动递增翻译的地址，并响应一个控制信号返回到翻译的地址。 连接到逻辑电路的控制电路响应于读取信号以将控制信号提供给逻辑电路。

公开(公告)号：US5493524A

公开(公告)日：1996-02-20

申请号：US426992

申请日：1995-04-24

Applicant: Karl M. Guttag ,  Richard D. Simpson ,  Brendan Walsh

Inventor： Karl M. Guttag ,  Richard D. Simpson ,  Brendan Walsh

IPC: G06F7/50 ,  G06F7/509 ,  G06F7/575 ,  G06F9/302 ,  G06F9/305

CPC classification number: G06F7/509 ,  G06F7/575 ,  G06F9/30014 ,  G06F9/30029

Abstract: A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The current instruction drives an instruction decoder (250, 245) that generates functions signals F0-F7 which control the combination formed. The three input arithmetic logic unit (230) preferably employs a set of bit circuits (400), each forming carry propagate, generate and kill signals. These signals and a carry input produce a bit resultant and a carry output to the next bit circuit. Selection of the function signals enables the combination to be insensitive to one of the input signals, thus performing a two input function of remaining input signals. The instruction itself may include the function signals and function modification bits, or the function signals and function modification signals may be stored in a special data register. Function modification signals cause modification of the function signals prior to use. The three input arithmetic logic unit (230) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit circuit (400). This carry input is determined by the combination being formed, and generally is "1" only during subtraction. The carry input may be specified in the special purpose data register (D0) for certain instructions.

Abstract translation: 三输入算术逻辑单元（230）形成三个多位输入信号的混合运算和布尔组合。 当前指令驱动产生控制所形成的组合的功能信号F0-F7的指令译码器（250,245）。 三输入算术逻辑单元（230）优选地采用一组比特电路（400），每一组形成进位传播，产生和终止信号。 这些信号和进位输入产生一个比特结果和一个进位输出到下一个比特电路。 功能信号的选择使得组合对输入信号之一不敏感，从而执行剩余输入信号的两个输入功能。 指令本身可以包括功能信号和功能修改位，或者功能信号和功能修改信号可以存储在特殊数据寄存器中。 功能修改信号在使用前会引起功能信号的修改。 三输入算术逻辑单元（230）包括向最低有效位电路（400）提供进位输入的最低有效位进位发生器（246）。 该进位输入由形成的组合确定，并且通常在减法期间为“1”。 某些指令可以在专用数据寄存器（D0）中指定进位输入。

公开(公告)号：US5270973A

公开(公告)日：1993-12-14

申请号：US563471

申请日：1990-08-06

Applicant: Andre J. Guillemaud ,  Anthony M. Balistreri ,  Karl M. Guttag ,  Richard D. Simpson

Inventor： Andre J. Guillemaud ,  Anthony M. Balistreri ,  Karl M. Guttag ,  Richard D. Simpson

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1006 ,  G11C7/1075

Abstract: A video random access memory includes memory cells arranged in rows and columns. The columns of memory cells are divided into first and second portions, and the cells of each row of the first portion of memory are interleaved by address with the cells of the same row of the second portion of memory. A first half of a serial register includes a plurality of storage elements that are interleaved by address with a plurality of storage elements of a second half of the serial register. Between the first and second portions of the memory cells, column leads and a multiplexer selectively couple data from either the first portion or the second portion of the columns of the memory cells to either the first half or the second half of the serial register.

Abstract translation: 视频随机存取存储器包括以行和列排列的存储单元。 存储器单元的列被分成第一和第二部分，并且存储器的第一部分的每行的单元通过与存储器的第二部分的同一行的单元的地址进行交织。 串行寄存器的前半部分包括多个存储元件，其通过地址与串行寄存器的后半部分的多个存储元件进行交织。 在存储器单元的第一和第二部分之间，列引线和多路复用器选择性地将数据从存储器单元的列的第一部分或第二部分耦合到串行寄存器的前半部分或后半部分。

公开(公告)号：US20080191910A1

公开(公告)日：2008-08-14

申请号：US12028469

申请日：2008-02-08

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: H03M7/16 ,  H03M1/12

CPC classification number: H03M7/16 ,  H03M7/165

Abstract: The present invention relates to Gray Codes and their conversion to sign and magnitude representation. Gray codes are used in flash ADCs (analogue to digital converters), which convert an analogue waveform into a sampled binary value. This can be done via a thermometer code, and the present invention addresses the issue of the propagation of error due to an indeterminant thermometer code value. In particular the invention provides a Gray code to sign and magnitude converter arranged to produce for the bits of its output other than the sign bit the same code for the Gray codes that are the same distance from the boundary where the sign bit changes value when the Gray codes are arranged in order of their value.

Abstract translation: 本发明涉及格雷码及其转换为符号和幅度表示。 格雷码用于闪存ADC（模数转换器），将模拟波形转换为采样二进制值。 这可以通过温度计代码来实现，并且本发明解决了由于不确定的温度计代码值导致的误差传播的问题。 特别地，本发明提供了一种格雷码，用于符号和幅度转换器，其被布置为产生除了符号位之外的其输出的比特，对于格雷码的相同代码，其与来自符号位改变值的边界相同的距离 格雷码按照它们的价值排列。

公开(公告)号：US5636335A

公开(公告)日：1997-06-03

申请号：US479478

申请日：1995-06-07

Applicant: Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

Inventor： Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

IPC: G06F3/14 ,  G09G1/16 ,  G09G5/00 ,  G09G5/06 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G06T15/60

CPC classification number: G06F3/1438 ,  G06F3/14 ,  G09G5/06 ,  G09G5/363 ,  G09G5/39 ,  G09G5/395 ,  G09G2360/126 ,  G09G5/001

Abstract: A graphics computer system including a host computer and a graphics processor. The host computer has a host data bus and a host address bus. A first video memory stores color codes corresponding to a display. The first video memory is connected to the host computer permitting it to specify the color codes. A first palette connected to the first video memory has a first look-up table memory for recalling color data words corresponding to color codes received from the first video memory. The first palette is connected to the host computer permitting it to specify the color data words stored in the first look-up table memory. The graphics processor has a local data bus and a local address bus. A second video memory stores color codes corresponding to a display, the graphics processor specifying the color codes stored in the second video memory. A second palette connected to the second video memory has a second look-up table memory. The second palette is connected to the graphics processor permitting it to specify the color data words stored in the second look-up table memory. An interface circuit connects to the host data bus, the host address bus and the second palette. The interface circuit writes data received from the host data bus into the second palette upon detecting predetermined addresses on the host address bus. This causes at least a portion of the second palette to store identical data as stored in corresponding locations of the first palette.

Abstract translation: 包括主计算机和图形处理器的图形计算机系统。 主机具有主机数据总线和主机地址总线。 第一视频存储器存储与显示相对应的颜色代码。 第一个视频存储器连接到主机，允许它指定颜色代码。 连接到第一视频存储器的第一调色板具有第一查找表存储器，用于调用与从第一视频存储器接收的彩色代码相对应的彩色数据字。 第一调色板连接到主计算机，允许其指定存储在第一查找表存储器中的颜色数据字。 图形处理器具有本地数据总线和本地地址总线。 第二视频存储器存储与显示相对应的颜色代码，图形处理器指定存储在第二视频存储器中的颜色代码。 连接到第二视频存储器的第二调色板具有第二查找表存储器。 第二调色板连接到图形处理器，允许其指定存储在第二查找表存储器中的颜色数据字。 接口电路连接到主机数据总线，主机地址总线和第二个调色板。 接口电路在检测到主机地址总线上的预定地址时，将从主机数据总线接收的数据写入第二调色板。 这导致第二调色板的至少一部分存储与存储在第一调色板的相应位置中相同的数据。

公开(公告)号：US5627568A

公开(公告)日：1997-05-06

申请号：US990971

申请日：1992-12-15

Applicant: Ian J. Sherlock ,  Richard D. Simpson ,  Michael D. Asal

Inventor： Ian J. Sherlock ,  Richard D. Simpson ,  Michael D. Asal

IPC: G09G5/36 ,  G09G5/39 ,  G09G5/00

CPC classification number: G09G5/39 ,  G09G5/363

Abstract: A display buffer includes a plurality of memory banks, each said bank having a plurality of ordered rows of data storage locations. Circuitry controls the storage of a plurality of sequenced lines of display data in said display buffer. A first set of lines of display data is stored at contiguous locations in a first memory bank with the first word of a first line being stored in a location offset from the first location of the first row so a last word of a last line is stored in the last location of the last row. A second set of lines is stored at contiguous locations starting at the first row of the second memory bank. A last line of the second set of lines is stored so that the last word of this last line is stored in the last location of a selected row of the second bank. A third set of lines is stored in a third memory bank starting at a memory line other than the first memory line. If additional space is needed, the display lines wrap around to the first location of the first line of the third bank of memories. A graphics processor may provide the memory addressing and bank selection logic.

Abstract translation: 显示缓冲器包括多个存储体，每个所述存储体具有多个排列的数据存储位置行。 电路控制在所述显示缓冲器中存储多条排序的显示数据行。 第一组显示数据被存储在第一存储体中的连续位置处，其中第一行的第一个字被存储在偏离第一行的第一位置的位置中，从而最后一行的最后一个字被存储 在最后一行的最后一个位置。 第二组线路存储在从第二存储器组的第一行开始的连续位置处。 存储第二组行的最后一行，使得最后一行的最后一个字被存储在第二组的所选行的最后位置。 第三组线路存储在从第一存储器线以外的存储线开始的第三存储体中。 如果需要额外的空间，则显示线缠绕到第三组存储器的第一行的第一位置。 图形处理器可以提供存储器寻址和存储体选择逻辑。