公开(公告)号：US20230071420A1

公开(公告)日：2023-03-09

申请号：US17874927

申请日：2022-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae In LEE ,  Byung Jin CHO ,  Jung Hoon LEE ,  Jaeduk LEE

IPC: H01L27/11582 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include a substrate, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate, and vertical channel structures provided in vertical channel holes penetrating the stack structure. Each of the vertical channel structures may include a data storage pattern covering an inner side surface of each of the vertical channel holes, a vertical semiconductor pattern covering the data storage pattern, and a gapfill insulating pattern filling an internal space enclosed by the vertical semiconductor pattern. The vertical semiconductor pattern may have a first surface which is in contact with the gapfill insulating pattern, and a second surface which is in contact with the data storage pattern. A germanium concentration in the vertical semiconductor pattern may decrease in a direction from the first surface toward the second surface.

公开(公告)号：US20220293632A1

公开(公告)日：2022-09-15

申请号：US17824821

申请日：2022-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyong PARK ,  Hyunseok NA ,  Jaeduk LEE

IPC: H01L27/11582 ,  H01L27/11556

Abstract: An integrated circuit device includes a plurality of conductive lines extending in a horizontal direction parallel to a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate, a plurality of insulation layers each between two adjacent conductive lines of the plurality of conductive lines to extend in the horizontal direction, a channel layer extending in the vertical direction in a channel hole passing through the plurality of conductive lines and the plurality of insulation layers, and a plurality of outer blocking dielectric layers between the plurality of conductive lines and the channel layer, in at least some of the plurality of conductive lines, wherein a width of each of the plurality of outer blocking dielectric layers in the horizontal direction increases toward the main surface.

公开(公告)号：US20220293180A1

公开(公告)日：2022-09-15

申请号：US17689005

申请日：2022-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk LEE ,  Kinam KIM ,  Sujin AHN

IPC: G11C16/04 ,  H01L27/11519 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11524

Abstract: Provided are semiconductor devices and data storage systems including the same. The semiconductor devices may include first and second separation structures parallel to each other, a block between the first and second separation structures, and bit lines on the block. The block includes strings, the bit lines include a first bit line electrically connected to first and second strings, each of the strings includes a lower select transistor, memory cell transistors, and upper select transistors connected in series, the upper select transistors in each of the strings include a first upper select transistor and a second upper select transistor below the first upper select transistor. The first upper select transistors of the first and second strings may share a single first upper select gate electrode. Gate electrodes of the lower select transistors of the first and second strings may include surfaces coplanar with each other.

公开(公告)号：US20170186758A1

公开(公告)日：2017-06-29

申请号：US15458273

申请日：2017-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun LEE ,  Dohyun LEE ,  Youngwoo PARK ,  Su Jin AHN ,  Jaeduk LEE

IPC: H01L27/11524 ,  G11C16/34 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/1157

CPC classification number: H01L27/11524 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16

Abstract: Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns. The three-dimensional semiconductor memory device further comprising a first ground selection transistor that includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor that includes a second gate pattern positioned on the first gate pattern and the first pillar, and wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.