公开(公告)号：EP1609180B1

公开(公告)日：2013-04-17

申请号：EP04722492.8

申请日：2004-03-22

Applicant: Silex Microsystems AB

Inventor： KÄLVESTEN, Edvard ,  EBEFORS, Thorbjörn ,  SVEDIN, Niklas ,  RANGSTEN, Pelle ,  HUHTAOJA, Tommy

IPC: B81B7/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: B81B7/0006 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05599

公开(公告)号：EP2377154A1

公开(公告)日：2011-10-19

申请号：EP09835356.8

申请日：2009-12-23

Applicant: Silex Microsystems AB

Inventor： EBEFORS, Thorbjörn ,  KÄLVESTEN, Edvard ,  ÅGREN, Peter ,  SVEDIN, Niklas

IPC: H01L23/522 ,  B61B7/00 ,  B81C1/00 ,  H01L21/768 ,  G02B26/08

CPC classification number: G02B26/0833 ,  B81B7/0006 ,  B81B7/007 ,  B81B2207/092 ,  B81B2207/095 ,  G02B6/3518 ,  G02B6/3584 ,  G02B26/0841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a layered micro-electronic and/or micro-mechanic structure, comprising at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.

公开(公告)号：EP1483196A1

公开(公告)日：2004-12-08

申请号：EP03705598.5

申请日：2003-02-14

Applicant: Silex Microsystems AB

Inventor： KÄLVESTEN, Edvard ,  EBEFORS, Thorbjörn ,  SVEDIN, Niklas ,  WESTIN, H kan

IPC: B81B3/00 ,  B81B7/04 ,  G02F1/29 ,  H01L21/00

CPC classification number: B81C1/0015 ,  B81B2201/042 ,  B81C1/00142 ,  B81C3/002 ,  B81C2201/019 ,  B81C2201/0191 ,  B81C2203/058

Abstract: The invention relates to a method of making a deflectable, free hanging micro structure comprising at least one hinge member, the method comprising the steps of providing a first sacrificial wafer comprising a single crystalline material constituting material forming the micro structure. A second semiconductor wafer comprising necessary components for forming the structure in cooperation with said first wafer is provided. Finite areas of a structured bonding material is provided, on one or both of said wafers at selected locations, said finite areas defining points of connection for joining said wafers. The wafers are bonded using heat and optionally pressure. Sacrificial material is etched away from said sacrificial wafer, patterning the top wafer by lithography is performed to define the desired deflectable microstructures having hinges, and subsequently silicon etch to make the structures.

公开(公告)号：EP2377154B1

公开(公告)日：2019-08-14

申请号：EP09835356.8

申请日：2009-12-23

Applicant: Silex Microsystems AB

Inventor： EBEFORS, Thorbjörn ,  KÄLVESTEN, Edvard ,  ÅGREN, Peter ,  SVEDIN, Niklas

IPC: G02B6/35 ,  H01L23/48 ,  G02B26/08 ,  B81C1/00 ,  H01L21/768 ,  B81B7/00

公开(公告)号：EP2365934A1

公开(公告)日：2011-09-21

申请号：EP09827830.2

申请日：2009-11-19

Applicant: Silex Microsystems AB

Inventor： EBEFORS, Thorbjörn ,  KÄLVESTEN, Edvard ,  BAUER, Thomas

IPC: B81C1/00 ,  B81B7/00 ,  H01L21/50 ,  H01L23/48

CPC classification number: H01L21/50 ,  B81B7/007 ,  B81B2207/095 ,  B81C1/00301 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/585 ,  H01L23/642 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29018 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/30051 ,  H01L2224/3012 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/3512

Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.

公开(公告)号：EP2121511A2

公开(公告)日：2009-11-25

申请号：EP08705365.8

申请日：2008-01-25

Applicant: Silex Microsystems AB

Inventor： EBEFORS, Thorbjörn ,  KÄLVESTEN, Edvard ,  BAUER, Tomas

IPC: B81B7/00 ,  B81C3/00 ,  H01L23/043

CPC classification number: H01L21/762 ,  B81C1/00246 ,  H01L21/823481 ,  H01L23/055 ,  H01L23/147 ,  H01L23/26 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6688 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A starting substrate in the form of a semiconductor wafer (1) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A1, A2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material (2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.

Abstract translation: 半导体晶片（1）形式的起始衬底具有第一侧和第二侧，所述侧面相对于彼此平行平行，并且具有使其适于处理的厚度，而没有显着的损坏风险， 为了制造组合的模拟和数字设计，晶片包括至少两个通过完全延伸穿过晶片的绝缘材料（2; 38; 81; L）彼此电绝缘的隔板（A1，A2; DIGITAL，ANALOGUE）。 还描述了用于制造包括晶片中的蚀刻沟槽以及用绝缘材料填充沟槽的这种衬底的方法。

公开(公告)号：EP1987535A1

公开(公告)日：2008-11-05

申请号：EP07709445.6

申请日：2007-01-31

Applicant: Silex Microsystems AB

Inventor： KÄLVESTEN, Edvard ,  BAUER, Tomas ,  EBEFORS, Thorbjörn

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/283 ,  H01L23/522

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to a method of providing a planar substrate with electrical through connections (vias). The method comprises providing a hole in said substrate and a treatment to render the substrate surface exhibiting a lower wettability than the walls inside the hole. The planar substrate is exposed to a molten material with low resistivity, whereby the molten material is drawn into the hole(s). It also relates to a semiconductor wafer as a starting substrate for electronic packaging applications, comprising low resistivity wafer through connections having closely spaced vias.

公开(公告)号：EP2365934B1

公开(公告)日：2019-03-27

申请号：EP09827830.2

申请日：2009-11-19

Applicant: Silex Microsystems AB

Inventor： EBEFORS, Thorbjörn ,  KÄLVESTEN, Edvard ,  BAUER, Thomas

IPC: B81C1/00 ,  B81B7/00 ,  H01L21/50 ,  H01L23/48

公开(公告)号：EP2005467B1

公开(公告)日：2018-07-11

申请号：EP07709446.4

申请日：2007-01-31

Applicant: Silex Microsystems AB

Inventor： KÄLVESTEN, Edvard ,  BAUER, Tomas ,  EBEFORS, Thorbjörn

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resistivity silicon base (110) having a high resistivity top layer (122) suitable for semiconductor engineering, characterized by having low resistivity wafer through connections (140).

公开(公告)号：EP1436582B1

公开(公告)日：2017-03-22

申请号：EP02778155.8

申请日：2002-10-15

Applicant: Silex Microsystems AB

Inventor： RANGSTEN, Pelle ,  KÄLVESTEN, Edvard ,  MECHBACH, Marianne

IPC: G01L9/00

CPC classification number: G01L9/0042 ,  G01L9/0055 ,  Y10T29/49002 ,  Y10T29/49004 ,  Y10T29/49007