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公开(公告)号：JPH06112471A
公开(公告)日：1994-04-22
申请号：JP28093792
申请日：1992-09-25
Applicant: SONY CORP
Inventor： ISHIDA MINORU
Abstract: PURPOSE:To enlarge a contact surface between a wiring and a diffustion layer in area so as to lessen contact resistance between them in a contact structure where the wiring and the diffusion layer are connected together through the intermediary of a contact hole provided to a layer insulating film. CONSTITUTION:As an example, a layer insulating film 14 is provided covering an N -diffusion layer 13 located at an upper part of a semiconductor substrate 11 (P well region 12), a contact hole 21 is provided to the insulating film 14 reaching to the inside of the N -diffusion layer 13 from above, a wiring 15 is formed inside the contact hole 21 and on the interlayer insulating film 14. Or, a contact hole (not shown in the figure) is provided penetrating the N - diffusion layer 13, an N -diffusion layer (not shown in a figure) is formed surrounding the contact hole concerned, and furthermore the wiring 15 is formed inside the contact hole and on the layer insulating film 14.
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公开(公告)号：JPH05299417A
公开(公告)日：1993-11-12
申请号：JP13184992
申请日：1992-04-23
Applicant: SONY CORP
Inventor： ISHIDA MINORU
IPC: H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/90
Abstract: PURPOSE:To facilitate the formation of a fine contact hole in a semiconductor device manufacturing process by forming an etching mask having a fine hole pattern. CONSTITUTION:First process: on the upper face of an insulating film 12 on a substrate 11 formed is an etching resistant film 13, having an etching resistance sufficiently larger than the insulating film 12 does. Second process: a resist film 14 is formed on the upper face of the etching resistant film 13, and then a first hole pattern 15 is formed in the resist film 14. Third process: a second hole pattern 16 is formed in the etching resistant film 13 by etching using the resist film 14 as etching mask. Forth process: the resist film 14 is removed, and then a contact hole 17 is formed in the insulating film 12 by etching using the etching resistant film 13 as etching mask.
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公开(公告)号：JPH0582784A
公开(公告)日：1993-04-02
申请号：JP27037491
申请日：1991-09-20
Applicant: SONY CORP
Inventor： ISHIDA MINORU
IPC: H01L29/78 , H01L21/336
Abstract: PURPOSE:To manufacture an MIS-type semiconductor device of good properties by restraining junction leak between a source/drain and a semiconductor substrate. CONSTITUTION:A gate electrode is formed of a polycrystalline Si film 16 and ion implantation of impurities is performed at low concentration for an Si substrate 11 using the polycrystalline Si film 16 as a mask, and an n layer 31 and a p layer 32 are formed of the impurities. A polycrystalline Si film 24 is patterned at both sides of the polycrystalline Si film 16, ion implantation of impurities is performed at high concentration for the polycrystalline Si film 24 and a source/drain is constituted of the polycrystalline Si film 24 and the n layer 31 or the p layer 32. Since ion implantation of impurities is performed only at a low concentration for the Si substrate 11 during formation of the n layer 31 and the p layer 32, little crystal defect is induced by the Si substrate 11.
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公开(公告)号：JPH056967A
公开(公告)日：1993-01-14
申请号：JP4254191
申请日：1991-02-13
Applicant: SONY CORP
Inventor： ISHIDA MINORU
IPC: H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/10 , H01L27/108
Abstract: PURPOSE:To reduce the number of wiring steps in a gate array which can place a DRAM by composing a gate of a MOS transistor and a trench capacitor, and connecting a drain to an electrode of a trench capacitor inside the trench by a wiring layer. CONSTITUTION:Each gate of this gate array has a structure in Fig. (A) at the stage before a wiring step, but when a MOS transistor of a logic circuit is formed at the gate, it is formed by a wiring step as shown in Fig. (B). That is, an interlayer insulating film 12 is formed on the surface of a semiconductor substrate, selectively etched to form a contact hole 11, and then electrodes 13d, 13g, 13s made of aluminum are formed. When a DRAM cell is formed at the gate, it is formed by a wiring step as shown in Fig. (C). That is, the film 12 is formed, and electrodes 13w, 13b made of aluminum are formed. Thus, the number of wiring steps can be reduced more.
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公开(公告)号：JPS62161252A
公开(公告)日：1987-07-17
申请号：JP29833985
申请日：1985-12-30
Applicant: SONY CORP
Inventor： KUSAKA SATORU , ISHIDA MINORU , WATANABE HIDEO
Abstract: PURPOSE:To record a desired image on an optional position on the optional size of recording paper face by controlling the sending of the image signal of an image signal sending section and the recording of the image of an image recording section on the recording paper based on a timing signal in response to the turning of a running roller. CONSTITUTION:The disk 20a of a rotary encoder 20 is turned by the turning of the running roller 14A and a timing pulse signal in response to the turning of the running roller 14A is obtained from the rotary encoder 20. A control circuit section applies the operation control of an image signal sending section and a thermosensing recording section 17 provided in a control block 19 based on the timing pulse signal from the rotary encoder 20. In the thermosensing recording section 17, the thermal heads arranged in its low end part 17a are operated sequentially in response to the image signal fed sequentially by the one line image and the recording of the line image by the thermosensing recording to the recording paper 21 is executed sequentially.
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Patent Agency Ranking26.发明专利
公开(公告)号：JP2014115863A
公开(公告)日：2014-06-26
申请号：JP2012270159
申请日：2012-12-11
Inventor： ISHIDA MINORU
CPC classification number: H04N5/2628 , H04N5/2258 , H04N5/23216 , H04N5/23238 , H04N5/23293
Abstract: PROBLEM TO BE SOLVED: To provide a user with an easily viewable image.SOLUTION: An information processing apparatus comprises an operation receiving unit, and a display control unit. When a plurality of images corresponding to a plurality of areas on a horizontally long image are displayed on a display unit, the operation receiving unit receives a predetermined operation with respect to at least one of the plurality of images. When the predetermined operation is received, the display control unit subjects each of the plurality of images to image processing corresponding to the predetermined operation, and controls the display unit to display each image subjected to the image processing.
Abstract translation: 要解决的问题：为用户提供容易观看的图像。解决方案：信息处理设备包括操作接收单元和显示控制单元。 当在显示单元上显示对应于水平长图像上的多个区域的多个图像时，操作接收单元接收关于多个图像中的至少一个的预定操作。 当接收到预定操作时，显示控制单元使多个图像中的每一个对应于预定操作的图像处理，并且控制显示单元显示经过图像处理的每个图像。
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27.发明专利
公开(公告)号：JP2014096809A
公开(公告)日：2014-05-22
申请号：JP2013254954
申请日：2013-12-10
Inventor： ISHIDA MINORU
Abstract: PROBLEM TO BE SOLVED: To properly display an image.SOLUTION: An information processor includes: a plurality of imaging sections and a display control section. The plurality of imaging sections are arranged in a direction almost orthogonal to a long side direction of a display section. The display control section controls display of an image to the display section. The display control section displays a plurality of regions on an almost rectangular image where a plurality of images generated by the plurality of imaging sections are coupled on the display section in a first display form where the number of stepwise stages in a gravity direction is set to be plural in a state where the long side direction of the display section becomes almost parallel to a gravity direction. An image including a region at a left end part in a long side direction of the almost rectangular image, an image including a region at a right end part in the long side direction, and an image including a region existing between both end parts in the long side direction are displayed on the display section as the plurality of regions on the almost rectangular image.
Abstract translation: 要解决的问题：正确显示图像。解决方案：信息处理器包括：多个成像部分和显示控制部分。 多个成像部分布置在与显示部分的长边方向几乎正交的方向上。 显示控制部控制向显示部显示图像。 显示控制部分在几何矩形图像上显示多个区域，其中由多个成像部分生成的多个图像以重力方向上的阶梯级数被设置为第一显示形式而在显示部分上耦合 在显示部的长边方向大致平行于重力方向的状态下为多个。 包括在近似矩形图像的长边方向上的左端部的区域的图像，包括在长边方向上的右端部的区域的图像，以及包括存在于长边方向的两端部之间的区域的图像 长边方向作为几乎矩形图像上的多个区域显示在显示部分上。
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公开(公告)号：JP2009177200A
公开(公告)日：2009-08-06
申请号：JP2009083754
申请日：2009-03-30
Inventor： ISHIDA MINORU
IPC: H01L21/8244 , H01L27/11
CPC classification number: H01L2224/4813 , H01L2924/13091 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To effectively prevent characteristic deterioration due to a pattern shift in gate formation while suppressing an increase in a cell area, and to reduce resistance in a power supply voltage feeder. SOLUTION: Two inverters respectively composed of first conductivity type driving transistors Qn1, Qn2 and second conductivity type load transistors Qp1, Qp2 which are electrically connected in series between a first power supply voltage feeder VSS and a second power supply voltage feeder VSS and of which gates are connected in common and cross-connecting inputs and outputs are included in each memory cell. At least one of the first power supply voltage feeder VSS and the second power supply voltage feeder VSS is composed of a groove wiring obtained by filling the inside of a through groove of an inter-layer insulating layer with a conductive material. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 解决的问题：为了有效地防止由于栅极形成中的图案偏移而导致的特性劣化，同时抑制单元面积的增加，并且降低电源电压馈线的电阻。 解决方案：两个反相器，分别由第一导电类型驱动晶体管Qn1，Qn2和第二导电类型负载晶体管Qp1，Qp2串联连接在第一电源电压馈线VSS和第二电源电压馈电器VSS之间，以及 其中各个门连接在共同的和交叉连接的输入和输出中，被包括在每个存储单元中。 第一电源电压馈线VSS和第二电源电压馈线VSS中的至少一个由通过用导电材料填充层间绝缘层的贯通槽的内部而获得的沟槽布线构成。 版权所有（C）2009，JPO＆INPIT
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公开(公告)号：JP2005252068A
公开(公告)日：2005-09-15
申请号：JP2004062131
申请日：2004-03-05
Inventor： ISHIDA MINORU , ARAYA KATSUHISA , KOCHIYAMA AKIRA , TSUSHIMA TOMOHITO
CPC classification number: G11C13/0011 , G11C11/5614 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/34 , G11C2213/79
Abstract: PROBLEM TO BE SOLVED: To enable easy and precise read-out of data by setting specific qualification, when writing is carried out to a selected storage cell. SOLUTION: In a storage cell 100, a structure is installed, in which an inter-electrode substance layer 13 is clamped between an electrode 11 (first electrode) and an electrode 12 (second electrode), and data are stored by variation of resistance value between the electrode 11 and the electrode 12. The resistance value is set to R_mem_high, when a storage element is in a state of high resistance; resistance value, when the storage element is in a state of low resistance, is set to R_mem_low1; the resistance value of a load circuit 111A is set to R_load; read-out voltage is set to Vread, when voltage of a second power source 107 is made reference voltage; and the threshold voltage is set to Vth_critical. When data are written to the storage cell, low resistance status is produced, by satisfying specific relations with these parameters. The load circuit 111A is also formed of an element, having the same structure with a storage element of the storage cell 100. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：当对所选存储单元进行写入时，通过设置特定的资格来实现对数据的简单和精确的读出。 解决方案：在存储单元100中，安装电极物质层13夹在电极11（第一电极）和电极12（第二电极）之间的结构，数据通过变化存储 电极11和电极12之间的电阻值。当存储元件处于高电阻状态时，电阻值被设定为R_mem_high; 当存储元件处于低电阻状态时，电阻值被设置为R_mem_low1; 负载电路111A的电阻值被设定为R_load; 当第二电源107的电压作为参考电压时，读出电压被设定为Vread; 并且阈值电压被设置为Vth_critical。 当将数据写入存储单元时，通过满足与这些参数的特定关系，产生低电阻状态。 负载电路111A也由具有与存储单元100的存储元件相同结构的元件形成。版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2001057033A
公开(公告)日：2001-02-27
申请号：JP23075099
申请日：1999-08-17
Applicant: SONY CORP
Inventor： ISHIDA MINORU
Abstract: PROBLEM TO BE SOLVED: To obtain a linear guide mechanism and an optical disk device which reduces resistance occurring with the movement of a movabIe part and which thereby enables its stable high-speed movement. SOLUTION: This is a linear guide mechanism that supports a movable part 27 movably in one direction against a fixed part 33, the movable part 27 being loaded with a light converging means 25 by which at least light from a light source is converged on the signal recording face of an optical disk D. The structure is such that the movable part 27 is provided on both sides with two inclined faces 31, 32 having a prescribed inclined angle, while the fixed part 33 is provided with two inclined faces 34, 35 corresponding to those 31, 32 of the movable part 27; that deformable belt-like supporting members 36, 37 are fixedly stored in a space formed by the pair of oppositely facing inclined faces of the movable part 27 and the fixed part 33; and that, by displacing each belt-like supporting members 36, 37 in the space, the movable part 27 is supported movably against the fixed part 33.
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