公开(公告)号：AT456921T

公开(公告)日：2010-02-15

申请号：AT07731846

申请日：2007-03-29

Applicant: FRANCE TELECOM

Inventor： LU JIA-LIANG ,  DOHLER MICHAEL ,  BARTHEL DOMINIQUE ,  VALOIS FABRICE

IPC: H04W84/20 ,  H04L12/56 ,  H04L29/12

Abstract: A system and method organize a network of communicating objects in at least one partition comprising a plurality of communication cells respectively covered by a plurality of leader nodes, the network having a set of allocatable addresses split into a plurality of address pools distributively managed by the leader nodes. Upon a new node arrival, phase (a) and possibly phase (b) are executed. During phase (a), if the new node detects a leader node, it allocates an address from its managed address pool and the new node assumes a member node roll in the leader node cell. If the new node does not detect any leader node in its vicinity, it goes on to the phase (b), wherein, if the new node detects a first cell member node, it assumes the role of leader covering a second cell, obtains an available pool of managed addresses and is allocated one of the obtained addresses.

公开(公告)号：FR2790832A1

公开(公告)日：2000-09-15

申请号：FR9902823

申请日：1999-03-08

Applicant: FRANCE TELECOM

Inventor： BARTHEL DOMINIQUE

IPC: G01R31/3185 ,  G01R31/26 ,  G01R31/317

Abstract: A method for testing an integrated circuit having memory elements which are written and/or read via an access path to the memory elements from a terminal external to the circuit. A boundary scan chain is activated to impose and/or observe logic levels on the integrated circuit inputs/outputs.