公开(公告)号：US11605424B2

公开(公告)日：2023-03-14

申请号：US17375945

申请日：2021-07-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anuj Grover ,  Tanmoy Roy ,  Nitin Chawla

IPC: G11C11/41 ,  G11C11/419 ,  H01L27/11

Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.