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公开(公告)号：US20170287394A1
公开(公告)日：2017-10-05
申请号：US15337185
申请日：2016-10-28
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： KWANG-MIN KIM , Won Kyu Kwak , Sun-Ja Kwon , Byung Sun Kim , Hye Jin Shin , Dong-Hyun Lee
IPC: G09G3/3225 , G09G3/3266 , G06F1/16
Abstract: A display device includes a display panel that includes a display area and a first peripheral area adjacent to the display area. The first peripheral area includes a bendable region extending across the display panel and a plurality of signal lines partially included in the bendable region. The plurality of signal lines includes a first and second group adjacent to each other in the bendable region. The first group includes two or more first signal lines that transmit signals of a first polarity. The second group includes two or more second signal lines that transmit signals of a second polarity different from the first polarity. The first and second group are separated by a first interval, and signal lines within the first or second group are separated by a second interval. The first interval is greater than the second interval.
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22.发明授权公开(公告)号：US09406730B2
公开(公告)日：2016-08-02
申请号：US14490725
申请日：2014-09-19
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Byoung-Keon Park , Jong-Ryuk Park , Yun-Mo Chung , Tak-Young Lee , Jin-Wook Seo , Ki-Yong Lee , Min-Jae Jeong , Yong-Duck Son , Byung-Soo So , Seung-Kyu Park , Dong-Hyun Lee , Kil-Won Lee , Jae-Wan Jung
CPC classification number: H01L27/3244 , H01L21/0245 , H01L21/02532 , H01L21/02667 , H01L21/02672 , H01L27/1277 , H01L27/3262 , H01L29/1033 , H01L29/66765 , H01L29/78609 , H01L29/78675 , H01L29/78678
Abstract: A method of forming a polycrystalline silicon layer includes forming a first amorphous silicon layer and forming a second amorphous silicon layer such that the first amorphous silicon layer and the second amorphous silicon layer have different film qualities from each other, and crystallizing the first amorphous silicon layer and the second amorphous silicon layer using a metal catalyst to form a first polycrystalline silicon layer and a second polycrystalline silicon layer. A thin film transistor includes the polycrystalline silicon layer formed by the method and an organic light emitting device includes the thin film transistor.
Abstract translation: 形成多晶硅层的方法包括：形成第一非晶硅层并形成第二非晶硅层，使得第一非晶硅层和第二非晶硅层彼此具有不同的膜质量，并使第一非晶硅层 以及使用金属催化剂形成第一多晶硅层和第二多晶硅层的第二非晶硅层。 薄膜晶体管包括通过该方法形成的多晶硅层和包括薄膜晶体管的有机发光器件。
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23.发明授权公开(公告)号：US09391292B2
公开(公告)日：2016-07-12
申请号：US14505391
申请日：2014-10-02
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Bo-Kyung Choi , Yun-Mo Chung , Jong-Ryuk Park , Jinwook Seo , Dong-Hyun Lee
CPC classification number: H01L51/5237 , H01L27/3244 , H01L27/3258 , H01L51/5209
Abstract: A display device includes a substrate, a passivation layer on the substrate and including an area having a first thickness and an area having a second thickness less than the first thickness, a first electrode on the passivation layer and including at least two sub-electrodes spaced apart from each other by a slit having two ends, a light emitting layer on the first electrode, and a second electrode on the light emitting layer. Both ends of the slit are in one the area of the passivation layer having the second thickness.
Abstract translation: 显示装置包括衬底，衬底上的钝化层，并且包括具有第一厚度的区域和具有小于第一厚度的第二厚度的区域;钝化层上的第一电极，并且包括间隔开的至少两个子电极 通过具有两端的狭缝彼此分开，在第一电极上的发光层和发光层上的第二电极。 狭缝的两端位于具有第二厚度的钝化层的一个区域中。
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公开(公告)号：US08987723B2
公开(公告)日：2015-03-24
申请号：US14056479
申请日：2013-10-17
Applicant: Samsung Display Co., Ltd.
Inventor： Byoung-Keon Park , Jin-Wook Seo , Ki-Yong Lee , Yun-Mo Chung , Jong-Ryuk Park , Tak-Young Lee , Dong-Hyun Lee , Kil-Won Lee , Byung-Soo So , Yong-Duck Son , Seung-Kyu Park , Jae-Wan Jung , Min-Jae Jeong
CPC classification number: H01L27/3262 , H01L27/12 , H01L27/1248 , H01L27/3258 , H01L27/326
Abstract: A display device including: a substrate; a first semiconductor layer disposed on the substrate; a second semiconductor layer disposed on the substrate and adjacent to the first semiconductor layer; a first insulation layer disposed on both the first semiconductor layer and the second semiconductor layer, the first insulation layer including a first opening forming a space between the first semiconductor layer and the second semiconductor layer; and a second insulation layer disposed on the first insulation layer and that fills the first opening.
Abstract translation: 一种显示装置，包括：基板; 设置在所述基板上的第一半导体层; 设置在所述基板上并与所述第一半导体层相邻的第二半导体层; 设置在第一半导体层和第二半导体层两者上的第一绝缘层，所述第一绝缘层包括在所述第一半导体层和所述第二半导体层之间形成空间的第一开口; 以及设置在第一绝缘层上并填充第一开口的第二绝缘层。
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25.发明申请METHOD OF MANUFACTURING THIN FILM TRANSISTOR,THIN FILM TRANSISTOR MANUFACTURED BY USING THE METHOD, METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS, AND ORGANIC LIGHT-EMITTING DISPLAY APPARATUS MANUFACTURED BY USING THE METHOD 审中-公开制造薄膜晶体管的方法，使用该方法制造的薄膜晶体管，制造有机发光显示装置的方法和使用该方法制造的有机发光显示装置公开(公告)号：US20140299860A1
公开(公告)日：2014-10-09
申请号：US14307980
申请日：2014-06-18
Applicant: Samsung Display Co., Ltd.
Inventor： Byoung-Keon Park , Jong-Ryuk Park , Dong-Hyun Lee , Jin-Wook Seo , Ki-Yong Lee
IPC: H01L27/32
CPC classification number: H01L27/3244 , H01L27/1288 , H01L27/3258 , H01L27/3262 , H01L29/0657 , H01L29/0847 , H01L29/41733 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/78606 , H01L29/78675 , H01L29/78696 , H01L2029/42388
Abstract: A method of manufacturing a thin film transistor (TFT) comprises forming a buffer layer, an amorphous silicon layer, and an insulating layer on a substrate; crystallizing the amorphous silicon layer as a polycrystalline silicon layer; forming a semiconductor layer and a gate insulating layer which have a predetermined shape by simultaneously patterning the polycrystalline silicon layer and the insulating layer; forming a gate electrode including a first portion and a second portion by forming and patterning a metal layer on the gate insulating layer. The first portion is formed on the gate insulating layer and overlaps a channel region of a semiconductor layer, and the second portion contacts the semiconductor layer. A source region and a drain region are formed on the semiconductor layer by doping a region of the semiconductor layer. The region excludes the channel region overlapping the gate electrode and constitutes a region which does not overlap the gate electrode. An interlayer insulating layer is formed on the gate electrode so as to cover the gate insulating layer; contact holes are formed on the interlayer insulating layer and the gate insulating layer so as to expose the source region and the drain region, and simultaneously an opening for exposing the second portion is formed. A source electrode and a drain electrode are formed by patterning a conductive layer on the interlayer insulating layer. The source electrode and the drain electrode are electrically connected to the source region and the drain region via the contact holes, and simultaneously the second portion exposed via the opening is removed.
Abstract translation: 制造薄膜晶体管（TFT）的方法包括在基板上形成缓冲层，非晶硅层和绝缘层; 使非晶硅层结晶为多晶硅层; 通过同时构图多晶硅层和绝缘层来形成具有预定形状的半导体层和栅极绝缘层; 通过在栅极绝缘层上形成和图案化金属层，形成包括第一部分和第二部分的栅电极。 第一部分形成在栅极绝缘层上并且与半导体层的沟道区重叠，并且第二部分接触半导体层。 通过掺杂半导体层的区域，在半导体层上形成源极区和漏极区。 该区域排除与栅电极重叠的沟道区域，并构成不与栅电极重叠的区域。 在栅电极上形成层间绝缘层，以覆盖栅极绝缘层; 在层间绝缘层和栅极绝缘层上形成接触孔，露出源极区域和漏极区域，同时形成露出第二部分的开口部。 源电极和漏电极通过在层间绝缘层上图案化导电层而形成。 源电极和漏电极经由接触孔电连接到源极区域和漏极区域，同时去除经由开口露出的第二部分。
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Patent Agency Ranking
公开(公告)号：US11849616B2
公开(公告)日：2023-12-19
申请号：US17930675
申请日：2022-09-08
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Keonwoo Kim , Deukjong Kim , Dong-Hyun Lee , Deok-Young Choi
IPC: H10K59/131 , H10K59/40 , H10K50/844 , H10K59/124 , H10K102/00
CPC classification number: H10K59/131 , H10K50/844 , H10K59/124 , H10K59/40 , H10K2102/00
Abstract: A display device includes first and second signal lines, first and second signal pads, and a pad insulating layer overlapping with the first and second signal lines. The first signal pad includes an intermediate conductive pattern overlapping with and connected to an end portion of the first signal line, and an upper conductive pattern on the intermediate conductive pattern, the upper conductive pattern being exposed through the pad insulating layer. The intermediate conductive pattern includes a first portion overlapping with the end portion of the first signal line, and a second portion between the end portion of the first signal line and an end portion of the second signal line and extending from the first portion. The upper conductive pattern is connected to the second portion of the intermediate conductive pattern.
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公开(公告)号：US20200321402A1
公开(公告)日：2020-10-08
申请号：US16813685
申请日：2020-03-09
Applicant: Samsung Display Co., Ltd.
Inventor： Byeongguk Jeon , Dong-Hyun Lee , Deok-Young Choi
Abstract: An electronic panel may include a plurality of sensing electrodes and a plurality of sensing lines. The sensing lines may include a plurality of first group sensing lines and a plurality of second group sensing lines, which are spaced apart from each other in a specific direction and are alternately arranged with respect to each other. Each of the first group sensing lines and the second group sensing lines may include a first pattern layer and a second pattern layer, which are spaced apart from each other with an insulating layer interposed therebetween and are coupled to each other through the insulating layer. Each of the first group sensing lines may include a first pattern layer in a specific region, and each of the second group sensing lines may include a second pattern layer in the specific region.
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公开(公告)号：US10147774B2
公开(公告)日：2018-12-04
申请号：US14307980
申请日：2014-06-18
Applicant: Samsung Display Co., Ltd.
Inventor： Byoung-Keon Park , Jong-Ryuk Park , Dong-Hyun Lee , Jin-Wook Seo , Ki-Yong Lee
IPC: H01L27/32 , H01L29/786 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/423 , H01L27/12 , H01L29/49 , H01L29/66
Abstract: A method of manufacturing a thin film transistor (TFT) comprises forming a buffer layer, an amorphous silicon layer, and an insulating layer on a substrate; crystallizing the amorphous silicon layer as a polycrystalline silicon layer; forming a semiconductor layer and a gate insulating layer which have a predetermined shape by simultaneously patterning the polycrystalline silicon layer and the insulating layer; forming a gate electrode including a first portion and a second portion by forming and patterning a metal layer on the gate insulating layer. The first portion is formed on the gate insulating layer and overlaps a channel region of a semiconductor layer, and the second portion contacts the semiconductor layer. A source region and a drain region are formed on the semiconductor layer by doping a region of the semiconductor layer. The region excludes the channel region overlapping the gate electrode and constitutes a region which does not overlap the gate electrode. An interlayer insulating layer is formed on the gate electrode so as to cover the gate insulating layer; contact holes are formed on the interlayer insulating layer and the gate insulating layer so as to expose the source region and the drain region, and simultaneously an opening for exposing the second portion is formed. A source electrode and a drain electrode are formed by patterning a conductive layer on the interlayer insulating layer. The source electrode and the drain electrode are electrically connected to the source region and the drain region via the contact holes, and simultaneously the second portion exposed via the opening is removed.
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29.发明授权Method and system for monitoring crystallization of amorphous silicon thin film, and method of manufacturing thin film transistor by using the method and system 有权用于监测非晶硅薄膜结晶的方法和系统，以及使用该方法和系统制造薄膜晶体管的方法公开(公告)号：US09257288B2
公开(公告)日：2016-02-09
申请号：US14022126
申请日：2013-09-09
Applicant: Samsung Display Co., LTD.
Inventor： Maidanchuk Ivan , Byung-Soo So , Dong-Hyun Lee , Won-Pil Lee
IPC: H01L21/66 , H01L21/268 , H01L21/00 , H01L21/02
CPC classification number: H01L21/268 , H01L21/02532 , H01L21/02667 , H01L22/12
Abstract: A method and system for monitoring crystallization of an amorphous silicon (a-Si) thin film, and a method of manufacturing a thin film transistor (TFT) by using the method and system are disclosed. The method of monitoring the crystallization of the a-Si thin film includes: irradiating light from a light source onto a monitoring a-Si thin film to anneal the monitoring a-Si thin film; annealing the monitoring a-Si thin film and concurrently measuring a Raman scattering spectrum of light scattered by the monitoring a-Si thin film at set time intervals; and calculating a crystallization characteristic value of the monitoring a-Si thin film based on the Raman scattering spectrum.
Abstract translation: 公开了一种用于监测非晶硅（a-Si）薄膜的结晶的方法和系统，以及通过使用该方法和系统制造薄膜晶体管（TFT）的方法。 监测a-Si薄膜结晶的方法包括：将来自光源的光照射到监测a-Si薄膜上，使监测a-Si薄膜退火; 对监测的a-Si薄膜进行退火，同时测量由监测a-Si薄膜以设定的时间间隔散射的光的拉曼散射光谱; 并基于拉曼散射光谱计算监测a-Si薄膜的结晶特征值。
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公开(公告)号：US12282238B2
公开(公告)日：2025-04-22
申请号：US18544332
申请日：2023-12-18
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Keonwoo Kim , Deukjong Kim , Dong-Hyun Lee , Deok-Young Choi
IPC: H10K59/131 , G02F1/1345 , H10K50/844 , H10K59/124 , H10K59/40 , H10K59/80 , H10K102/00
Abstract: A display device includes first and second signal lines, first and second signal pads, and a pad insulating layer overlapping with the first and second signal lines. The first signal pad includes an intermediate conductive pattern overlapping with and connected to an end portion of the first signal line, and an upper conductive pattern on the intermediate conductive pattern, the upper conductive pattern being exposed through the pad insulating layer. The intermediate conductive pattern includes a first portion overlapping with the end portion of the first signal line, and a second portion between the end portion of the first signal line and an end portion of the second signal line and extending from the first portion. The upper conductive pattern is connected to the second portion of the intermediate conductive pattern.
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