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公开(公告)号:US11436173B2
公开(公告)日:2022-09-06
申请号:US17233677
申请日:2021-04-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Win Naing Maung , Bhupendra Sharma , Huanzhang Huang , Douglas Edward Wente , Suzanne Mary Vining , Mustafa Ulvi Erdogan
Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.
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公开(公告)号:US11356236B2
公开(公告)日:2022-06-07
申请号:US16827415
申请日:2020-03-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Win Naing Maung , Charles Michael Campbell
Abstract: Circuit including a first port to couple to a first device; a second port to couple to a second device; a first channel having an input coupled to first port and an output coupled to second port, the first channel to re-drive a signal and output re-driven signal; a second channel having an input coupled to second port and an output coupled to first port, the second channel to re-drive a signal and output re-driven signal; and a controller to: enable first channel and disable second channel responsive to detecting a signal edge at first port; enable second channel and disable first channel responsive to detecting a signal edge at second port; sample impedance at first port if signal received at first port is de-asserted while first channel is enabled; and sample impedance at second port if signal received at second port is de-asserted while second channel is enabled.
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公开(公告)号:US20220137695A1
公开(公告)日:2022-05-05
申请号:US17577688
申请日:2022-01-18
Applicant: Texas Instruments Incorporated
Inventor: Suzanne Mary Vining , Douglas Edward Wente , Win Naing Maung , Julie Marie Nirchi
IPC: G06F1/3234 , G06F13/42 , G06F1/3206 , G06F13/40
Abstract: In an example, a data communication device includes one or more receivers, and one or more transmitters. The data communication device detects a start of frame packet (μSOF) on a data bus, wherein the μSOF indicates the start of a microframe; determines whether there are any data packets contained in the microframe during a first threshold period after the μSOF; and detects that there is no data packet contained in the microframe during the first threshold period after the μSOF, and in response, transitions at least one of the one or more transmitters from an active state to an OFF state, and transitions the at least one of the one or more transmitters from the OFF state to the active state prior to a switchback period before the end of the microframe.
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公开(公告)号:US11281284B2
公开(公告)日:2022-03-22
申请号:US16717836
申请日:2019-12-17
Applicant: Texas Instruments Incorporated
Inventor: Suzanne Mary Vining , Douglas Edward Wente , Win Naing Maung , Julie Marie Nirchi
IPC: G06F1/3234 , G06F13/42 , G06F1/3206 , G06F13/40
Abstract: A method includes detecting a micro start of frame packet (μSOF) on a data bus. If there is at least one data packet contained in a microframe during the first threshold period after the μSOF, transmitters are held in an active state. If there is no data packet in the first threshold period after the μSOF, the transmitters are transitioned from the active state to an OFF state. The method also includes transitioning the transmitters from the OFF state to the active state prior to a switchback period before the end of the microframe. The method also includes transitioning the transmitters from the OFF state to the active state if a data packet is received in the OFF state. The method also includes dropping the data packet received in the OFF state and transitioning from the OFF state to the active state when the data packet is dropped.
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公开(公告)号:US11133841B2
公开(公告)日:2021-09-28
申请号:US16778864
申请日:2020-01-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Suzanne Mary Vining , Gary Chard , Win Naing Maung , Mark Alan McAdams
Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.
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公开(公告)号:US20210250026A1
公开(公告)日:2021-08-12
申请号:US17174119
申请日:2021-02-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Win Naing Maung , Bharath Kumar Singareddy , Soumi Paul , Mayank Garg , Suzanne Mary Vining
IPC: H03K19/0185 , H04L7/00
Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.
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公开(公告)号:US11010319B2
公开(公告)日:2021-05-18
申请号:US15931762
申请日:2020-05-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Win Naing Maung , Bhupendra Sharma , Huanzhang Huang , Douglas Edward Wente , Suzanne Mary Vining , Mustafa Ulvi Erdogan
Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.
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公开(公告)号:US10657090B2
公开(公告)日:2020-05-19
申请号:US16716891
申请日:2019-12-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Win Naing Maung , Bhupendra Sharma , Huanzhang Huang , Douglas Edward Wente , Suzanne Mary Vining , Mustafa Ulvi Erdogan
Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.
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公开(公告)号:US20250021514A1
公开(公告)日:2025-01-16
申请号:US18903010
申请日:2024-10-01
Applicant: Texas Instruments Incorporated
Inventor: Win Naing Maung , Suzanne Mary Vining
IPC: G06F13/42 , G06F1/3206 , G06F13/38
Abstract: A serial bus repeater includes a port circuit and a low power state detection circuit. The port circuit is configured to communicate via a serial bus. The low power state detection circuit includes a power state transaction identification circuit and a bus state identification circuit. The power state transaction identification circuit is configured to identify a power state transaction on the serial bus. The power state transaction is indicative of entering a reduced power state. The bus state identification circuit is configured to identify a value of termination resistance on the serial bus that is indicative of entering the reduced power state.
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公开(公告)号:US20240396554A1
公开(公告)日:2024-11-28
申请号:US18792708
申请日:2024-08-02
Applicant: Texas Instruments Incorporated
Inventor: Win Naing Maung , Bharath Kumar Singareddy , Soumi Paul , Mayank Garg , Suzanne Mary Vining
IPC: H03K19/0185 , G06F13/42 , H04B3/36 , H04L7/00 , H04L25/02
Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.
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