公开(公告)号：US20240072025A1

公开(公告)日：2024-02-29

申请号：US17893312

申请日：2022-08-23

Applicant: Texas Instruments Incorporated

Inventor： Rajen M. Murugan ,  Yiqi Tang ,  Jie Chen ,  Ramlah Abdul Razak

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/367 ,  H01L23/552

CPC classification number: H01L25/165 ,  H01L23/3675 ,  H01L23/552 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48195 ,  H01L2224/73265 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/17787 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025

Abstract: An example semiconductor package comprises a ceramic header having a first open space separated from a second open space by a ceramic barrier. A first heat sink is attached to a bottom of the ceramic header below the first open area. A first integrated circuit (IC) die is mounted on the first heat sink. A second heat sink is attached to a bottom of the ceramic header below the second open area. A second IC die is mounted on the second heat sink. A capacitive interface is disposed in the ceramic barrier between the first IC die and the second IC die. The capacitive has a plurality of capacitive elements alternating with a plurality of shielding elements. The capacitive elements are tunable over a range of capacitive values.

公开(公告)号：US11881460B2

公开(公告)日：2024-01-23

申请号：US18172208

申请日：2023-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Li Jiang ,  Rajen Manicon Murugan

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/58 ,  H01L21/50 ,  H01L21/52

CPC classification number: H01L23/585 ,  H01L21/50 ,  H01L21/52 ,  H01L23/552 ,  H01L23/562 ,  H01L23/564

Abstract: In examples, a semiconductor package comprises a ceramic substrate and first and second metal layers covered by the ceramic substrate. The first metal layer is configured to carry signals at least in a 20 GHz to 28 GHz frequency range. The package comprises a semiconductor die positioned above the first and second metal layers and coupled to the first metal layer. The package comprises a ground shield positioned in a horizontal plane between the semiconductor die and the first metal layer, the ground shield including an orifice above a portion of the first metal layer. The package includes a metal seal ring coupled to a top surface of the ceramic substrate, the metal seal ring having a segment that is vertically aligned with a segment of the ground shield. The segment of the ground shield is between the orifice of the ground shield and a horizontal center of the ground shield. The package comprises a metal lid coupled to a top surface of the metal seal ring.

公开(公告)号：US20240006267A1

公开(公告)日：2024-01-04

申请号：US17809808

申请日：2022-06-29

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Yiqi Tang ,  Jie Chen ,  Rajen M. Murugan

IPC: H01L23/433 ,  H01L23/15 ,  H01L23/13 ,  H01L21/48

CPC classification number: H01L23/433 ,  H01L23/15 ,  H01L23/13 ,  H01L21/4882 ,  H01L24/16

Abstract: An example semiconductor package comprises a ceramic header having a top surface and a cavity formed within the ceramic header. The cavity is open at the top surface. A semiconductor die is mounted within the cavity of the ceramic header. A lid structure is coupled to the top surface of the ceramic header. The lid structure and ceramic header form a portion of a package enclosing the semiconductor die. One or more silver tubes are in contact with a first surface of the semiconductor die and with a first surface of the lid structure. A seal ring is located between the top surface of the ceramic header and the lid structure. The seal ring couples the lid structure to the ceramic header. The one or more silver tubes are hollow and filled with a getter material.

公开(公告)号：US20230207430A1

公开(公告)日：2023-06-29

申请号：US18177273

申请日：2023-03-02

Applicant: Texas Instruments Incorporated

Inventor： Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49534 ,  H01L23/49589 ,  H01L23/49558 ,  H01L23/49575 ,  H01L21/565 ,  H01L21/563 ,  H01L21/4821 ,  H01L24/16 ,  H01L23/3107 ,  H01L2224/16245

Abstract: A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

公开(公告)号：US11587899B2

公开(公告)日：2023-02-21

申请号：US16941818

申请日：2020-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Naweed Anjum ,  Liang Wan ,  Michael Gerald Amaro

IPC: H01L21/44 ,  H01L23/52 ,  H01L23/00 ,  H01L23/58 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

公开(公告)号：US20220209391A1

公开(公告)日：2022-06-30

申请号：US17138557

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Makarand Ramkrishna Kulkarni ,  Liang Wan ,  Rajen Manicon Murugan

IPC: H01Q1/22 ,  H01Q9/04 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01P3/08

Abstract: An antenna in package (AIP) 400 includes an IC die 120 including bond pads 121 and a package substrate including the IC die mounted up and being completely embedded therein. The package substrate includes a top layer 418 including a top dielectric layer 418b, a top metal layer 418a including an antenna 418a1, and a bottom layer 415 including a bottom dielectric 415b and a bottom metal layer 415a including contact pads including a first contact pad 415a1, and filled vias 415c, 417c. The bond pads are electrically coupled by a connection including a filled via(s) for connecting to the top metal layer and/or the bottom metal layer. Metal pillars including a first metal pillar 132a are electrically are coupled to the first contact pad, and at least one filled via is electrically coupled to the first metal pillar for providing a transmission line from the first contact pad to the antenna.

公开(公告)号：US20220028770A1

公开(公告)日：2022-01-27

申请号：US17227722

申请日：2021-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L23/498 ,  H01L21/48 ,  H02M1/00

Abstract: A semiconductor device includes a die with a power converter module. The power converter module includes an output port and a return port. The semiconductor device also includes a connection assembly that includes pads configured to be coupled to circuit components of a printed circuit board (PCB). The connection assembly also includes a first layer patterned to include a first trace that is coupled to one of the output port and the return port and a second trace that is coupled to the other of the output port and return port. A second layer of the connection assembly is patterned to provide a first via between the first trace and a third layer and a second via between the first trace and the third layer. The third layer is patterned to provide a portion of a first conductive path and a portion of a second conductive path.

公开(公告)号：US20220028593A1

公开(公告)日：2022-01-27

申请号：US17383878

申请日：2021-07-23

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Jonathan Almeria Noquil

IPC: H01F17/00 ,  H01L23/495 ,  H05K1/16 ,  H01L23/522 ,  H01F27/28 ,  H01L23/498 ,  H01L21/56 ,  H01F41/04

Abstract: An electronic device includes a multilevel package substrate, conductive leads, a die, and a package structure. The multilevel package substrate has a first level, a second level, and a third level, each having patterned conductive features and molded dielectric features. The first level includes a first patterned conductive feature with multiple turns that form a first winding. The second level includes a second patterned conductive feature, and the third level includes a third patterned conductive feature with multiple turns that form a second winding. A first terminal of the die is coupled to the first end of the first winding, a second terminal of the die is coupled to the second end of the first winding, and a third terminal of the die is coupled to a first conductive lead. The package structure encloses the first die, the second die, and a portion of the multilevel package substrate.

公开(公告)号：US20210327829A1

公开(公告)日：2021-10-21

申请号：US16850620

申请日：2020-04-16

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/495 ,  H01L33/62 ,  H01L23/00 ,  H01L33/00

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US20250140708A1

公开(公告)日：2025-05-01

申请号：US18987433

申请日：2024-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Liang Wan ,  Makarand Ramkrishna Kulkarni ,  Jie Chen ,  Steven Alfred Kummerl

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.