公开(公告)号：US10897131B2

公开(公告)日：2021-01-19

申请号：US15878421

申请日：2018-01-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Liao ,  Ting-Yao Lin ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H02H9/00 ,  H02H9/04 ,  H02H1/00 ,  H01L27/02 ,  H01L27/06

Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.

公开(公告)号：US20200381415A1

公开(公告)日：2020-12-03

申请号：US16446599

申请日：2019-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Wei Tseng ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02

Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.

公开(公告)号：US20190273077A1

公开(公告)日：2019-09-05

申请号：US15927107

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun Chiang ,  Ying-Wei Tseng ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L23/60 ,  H01L23/10 ,  G01R31/28 ,  G01R31/00

Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.

公开(公告)号：US10262940B2

公开(公告)日：2019-04-16

申请号：US15667637

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/522

Abstract: An electric connector includes a metal interconnect, a first vertical element and a second vertical element. The metal interconnect includes a plurality of horizontal elements. The first vertical element physically connects to a top surface of each of the horizontal elements. The second vertical element physically connects to a bottom surface of each of the horizontal elements, and the second vertical element misaligns the first vertical element. The present invention also provides an electric connector including a first vertical element and a second vertical element. The first vertical element physically connects to a top surface of a horizontal element. The second vertical element physically connects to a bottom surface of the horizontal element, and the second vertical element misaligns the first vertical element, wherein the first vertical element or the horizontal element is burned out before the second vertical element is burned out while a voltage is applied.

公开(公告)号：US10204897B2

公开(公告)日：2019-02-12

申请号：US15484143

申请日：2017-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a doped region formed in the source region. The source region and the drain region include a first conductivity type, and the doped region includes a second conductivity type complementary to the first conductivity type. The doped region is electrically connected to a ground potential.

公开(公告)号：US10103136B2

公开(公告)日：2018-10-16

申请号：US15464362

申请日：2017-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region. The gate set includes at least a first gate structure, a second gate structure, and a third gate structure.

公开(公告)号：US10090291B2

公开(公告)日：2018-10-02

申请号：US15138226

申请日：2016-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: A layout structure of an ESD protection semiconductor device includes a substrate, a first doped region, a pair of second doped regions, a pair of third doped regions, at least a first gate structure formed within the first doped region, and a drain region and a first source region formed at two sides of the first gate structure. The substrate, the first doped region and the third doped regions include a first conductivity type. The second doped regions, the drain region and the first source region include a second conductivity type complementary to the first conductivity type. The first doped region includes a pair of lateral portions and a pair of vertical portions. The pair of second doped regions is formed under the pair of lateral portions, and the pair of third doped regions is formed under the pair of vertical portions.

公开(公告)号：US20180269198A1

公开(公告)日：2018-09-20

申请号：US15983113

申请日：2018-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Chen Chang

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0255 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/78 ,  H01L29/7818 ,  H01L29/7831 ,  H01L29/7835

Abstract: An electrostatic discharge (ESD) protection device includes a substrate, a first gate group and a second gate group on the substrate, a drain region and a fourth doped region respectively at two sides of the first gate group, a source region and the fourth doped region respectively at two sides of the second gate group, a first doped region in the substrate and surrounded by the drain region, and a second doped region in the substrate and surrounded by the fourth doped region. The drain region and the source region have a first conductivity type. The first doped region and the second doped region have a second conductivity type complementary to the first conductivity type. The drain region is electrically connected to an input/output pad. The source region is electrically connected to a ground pad. The first doped region and the second doped region are electrically connected to each other.

公开(公告)号：US10008489B2

公开(公告)日：2018-06-26

申请号：US14724825

申请日：2015-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Chen Chang

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0255 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/78 ,  H01L29/7818 ,  H01L29/7831 ,  H01L29/7835

Abstract: An electrostatic discharge protection semiconductor device includes a substrate, a gate set positioned on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the drain region, and at least a second doped region formed in the substrate. The source region and the drain region include a first conductivity type, the first doped region and the second doped region include a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other. The first doped region and the second doped region are electrically connected to each other.

公开(公告)号：US20180138166A1

公开(公告)日：2018-05-17

申请号：US15351413

申请日：2016-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7835

Abstract: A semiconductor device for ESD protection, includes a drain region, a first doped region, a second doped region and a source region. The drain region is disposed in a substrate at a first side of a gate and the drain region has a first conductivity type. The first doped region is disposed in a second doped well at a second side of the gate and has a second conductivity type. The source region is also disposed in the second doped well and has the first conductive type, and the source region surrounds the first doped region from a topview. The second doped region is disposed in the second doped well and has the second conductive type, and the second doped region is disposed between the gate and the source region, wherein a plurality of contacts is electrically connected to the second doped region.