公开(公告)号：WO2010076187A3

公开(公告)日：2010-07-08

申请号：PCT/EP2009/067156

申请日：2009-12-15

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto ,  GIRLANDO, Giovanni

Inventor： PAGANI, Alberto ,  GIRLANDO, Giovanni

IPC: H01L23/66 ,  H01L23/48 ,  H01L21/66 ,  H01L23/544 ,  H01L25/065

Abstract: An integrated electronic device (1) having a body (9) of semiconductor material and a first antenna (3;3a) which enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna (3b,3c). The integrated electronic device (1) has a first via (4;4a- 4d;50;50a;53) of magnetic material arranged at least in part inside the body (9), which forms, in use, a communication channel between the first antenna (3;3a) and the further antenna (3b,3c).

公开(公告)号：WO2010046724A1

公开(公告)日：2010-04-29

申请号：PCT/IB2008/003660

申请日：2008-10-22

Applicant: STMICROELECTRONICS (GRENOBLE) SAS ,  STMICROELECTRONICS S.R.L. ,  TENUCCI, Sergio ,  PAGANI, Alberto ,  SPINETTA, Marco ,  RANCHOUX, Bernard

Inventor： TENUCCI, Sergio ,  PAGANI, Alberto ,  SPINETTA, Marco ,  RANCHOUX, Bernard

IPC: G05B19/418 ,  G01R31/28

CPC classification number: G05B19/41875 ,  G01R31/2894 ,  Y02P90/22 ,  Y02P90/86

Abstract: The invention relates to a method for an improved checking of repeatability and reproducibility of a measuring chain, in particular for the quality control by means of the semiconductor device testing, wherein testing steps are provided for multiple and different devices to be subjected to measurement through a measuring system comprising at least one concatenation of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement. Advantageously, the method comprises the following steps: checking repeatability and reproducibility of each type of unit that forms part of the measuring chain of the concatenation; then making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement.

Abstract translation: 本发明涉及一种用于改进测量链的重复性和再现性检查的方法，特别是通过半导体器件测试进行质量控制的方法，其中为多个和不同的器件提供测试步骤以通过 测量系统包括测试装置（ATE）和待测量的每个装置之间的测量单元的至少一个级联。 有利地，该方法包括以下步骤：检查构成级联测量链的一部分的每种类型的单元的重复性和重复性; 然后在各测量链之间进行整体的相关性，以检查重复性和再现性，使用相应的测量装置。

公开(公告)号：WO2008064994A1

公开(公告)日：2008-06-05

申请号：PCT/EP2007/062246

申请日：2007-11-13

Applicant: STMICROELECTRONICS S.R.L. ,  MAURO, Sergio Riccardo ,  FABIANO, Sergio

Inventor： MAURO, Sergio Riccardo ,  FABIANO, Sergio

IPC: H04L25/49

CPC classification number: H04L25/49

Abstract: A regulation and shaping circuit comprising a first input terminal (405) for receiving a first input signal (Vref) with a first frequency; a second input terminal (410) for receiving a second input signal (Vin1) with a second frequency higher than the first frequency; a first circuital branch (420) coupled to the first input terminal and, through first coupling means (Z2) active at the first frequency, to an output terminal (415) for providing an output signal (Vout1); a second circuital branch (425) coupled to the second input terminal and to the output terminal, wherein said second circuital branch comprises a negative feedback circuital loop (430, 435) adapted to control the output signal according to the second input signal.

Abstract translation: 一种调节和整形电路，包括用于接收具有第一频率的第一输入信号（Vref）的第一输入端（405） 用于接收具有高于第一频率的第二频率的第二输入信号（Vin1）的第二输入端（410） 耦合到第一输入端的第一电路分支（420），以及通过第一频率的第一耦合装置（Z2）连接到用于提供输出信号（Vout1）的输出端（415）; 耦合到第二输入端和输出端的第二电路分支（425），其中所述第二电路分支包括适于根据第二输入信号控制输出信号的负反馈电路回路（430,435）。

公开(公告)号：WO2008018095A1

公开(公告)日：2008-02-14

申请号：PCT/IT2006/000607

申请日：2006-08-07

Applicant: STMicroelectronics s.r.l. ,  ADRAGNA Claudio

Inventor： ADRAGNA Claudio

IPC: G05F1/70 ,  H02M1/00

CPC classification number: G05F1/70

Abstract: A control device for a power factor correction device in forced switching power supplies is disclosed; the device for correcting the power factor comprises a converter (20) and said control device (1) is coupled with the converter to obtain from an input alternating line voltage (Vin) a regulated output voltage (Vout). The converter (20) comprises a power transistor (M) and the control device (1) comprises a driving circuit (3, 4, 6, 10) of said power transistor; the driving circuit comprises a timer (130) suitable for setting the switch-off period of said power transistor (M). The timer is coupled with the alternating line voltage (Vin) in input to the converter and is suitable for determining the switch-off period of the power transistor in function of the value of the alternating line voltage (Vin) in input to the converter.

Abstract translation: 公开了一种用于强制开关电源中的功率因数校正装置的控制装置; 用于校正功率因数的装置包括转换器（20），并且所述控制装置（1）与转换器耦合以从输入交流线电压（Vin）获得调节输出电压（Vout）。 所述转换器（20）包括功率晶体管（M），所述控制装置（1）包括所述功率晶体管的驱动电路（3,4,6,10） 所述驱动电路包括适于设置所述功率晶体管（M）的关断周期的定时器（130）。 定时器与输入到转换器的交流线路电压（Vin）耦合，适用于根据输入到转换器的交流线路电压（Vin）的值来确定功率晶体管的关断周期。

公开(公告)号：WO2008012342A1

公开(公告)日：2008-01-31

申请号：PCT/EP2007/057706

申请日：2007-07-26

Applicant: STMICROELECTRONICS S.R.L. ,  PELLIZZER, Fabio ,  BEZ, Roberto ,  BEDESCHI, Ferdinando ,  GASTALDI, Roberto

Inventor： PELLIZZER, Fabio ,  BEZ, Roberto ,  BEDESCHI, Ferdinando ,  GASTALDI, Roberto

IPC: H01L27/24 ,  G11C16/02

CPC classification number: G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144

Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.

Abstract translation: 一种具有由相变存储元件（3）和选择开关（4）形成的存储单元（2）的相变存储器件。 由自己的相变存储元件（3）和自己的选择开关（4）形成的参考单元（2a）与待读取的存储单元组（7）相关联。 将该组存储器单元的电量与参考单元的类似电量进行比较，由此补偿存储单元的特性中的任何漂移。

公开(公告)号：WO2007141811A3

公开(公告)日：2007-12-13

申请号：PCT/IT2006/000420

申请日：2006-06-06

Applicant: STMicroelectronics S.r.l. ,  FROSINI Andrea ,  FISCHETTI Alessandra

Inventor： FROSINI Andrea ,  FISCHETTI Alessandra

IPC: C12Q1/68

Abstract: A process for preparing a semiconductor substrate for biological analysis in an integrated device, the biological analysis comprising the steps of amplifying DNA and detecting amplified DNA in the same chamber, comprises the steps of a) forming a silicon dioxide surface on said semiconductor substrate b) treating said silicon dioxide surface with a silane; c) forming a silanized surface; d) grafting nucleic acid probes; e) treating said silanized surface with a deactivating agent and f) forming a deactivated substrate sequentially. Further the process can include the step of cleaning the silicon dioxide substrate before the step of treating said silicon dioxide surface with a silane and the step of reacting the terminal group of the silane with a cross-linker or alternatively the step of reacting the derivatized nucleic acid probes with a cross-linker, before the grafting step.

公开(公告)号：WO2007108017A1

公开(公告)日：2007-09-27

申请号：PCT/IT2006/000170

申请日：2006-03-20

Applicant: STMicroelectronics S.r.l. ,  ROLANDI, Paolo ,  CALLIGARO, Cristiano ,  PASCUCCI, Luigi

Inventor： ROLANDI, Paolo ,  CALLIGARO, Cristiano ,  PASCUCCI, Luigi

IPC: H01L29/78 ,  H01L27/06 ,  H01L27/115 ,  H01L27/12 ,  H01L21/822

CPC classification number: H01L27/11551 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/7832

Abstract: Semiconductor device (1; 38, 48) formed by a first conductive strip (10) of semiconductor material; a control gate region (7; 35; 55) of semiconductor material, facing a channel portion (5c) of the first conductive strip,- and an insulation region (6; 32; 52) arranged between the first conductive strip and the control gate region. The first conductive strip (10) includes a conduction line (5) having a first conductivity type and a control line (4) having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line (5) forms the channel portion (5c) , a first conduction portion (5a) and a second conduction portion (5b) arranged on opposite sides of the channel portion.

Abstract translation: 由半导体材料的第一导电条（10）形成的半导体器件（1; 38,48） 面对第一导电带的沟道部分（5c）的半导体材料的控制栅极区域（7; 35; 55）以及布置在第一导电带和控制栅极之间的绝缘区域（6; 32; 52） 地区。 第一导电条（10）包括具有第一导电类型的导线（5）和具有第二导电类型的控制线（4），彼此相邻并且彼此电接触，导线（5）形成 通道部分（5c），布置在通道部分的相对侧上的第一导电部分（5a）和第二导电部分（5b）。

公开(公告)号：WO2007096920A1

公开(公告)日：2007-08-30

申请号：PCT/IT2006/000117

申请日：2006-02-27

Applicant: STMICROELECTRONICS S.r.l. ,  CESURA, Giovanni Antonio ,  MASSOLINI, Roberto Giampiero

Inventor： CESURA, Giovanni Antonio ,  MASSOLINI, Roberto Giampiero

IPC: H03M1/10 ,  H03M1/40 ,  H03M1/44 ,  H03M1/16

CPC classification number: H03M1/1061 ,  H03M1/1004 ,  H03M1/162 ,  H03M1/164 ,  H03M1/40 ,  H03M1/44

Abstract: Multistage ADC (1) for converting in multi- step cycles, analogue samples (V] n) of an input signal (VIn) into digital codes (Dout) each cycle resolving at least one bit of digital code (Dout), the converter (1) including: - a generation block (3) of a pseudorandom sequence (Y' ts) to be summed to said analogue samples, obtaining a second sequence ( V+in) of analog samples; - conversion means (5) with controllable digital gain ( g ), receiving the second sequence (V+in) and outputting bits of said digital codes (Dout); - a feedback loop (2, 6, 7, 8) for performing said multi- step conversion cycles, with a loop gain (GLoop); - a digital calibration block (9) matching the digital gain ( g ) to the loop gain ( GLoop ); said second sequence (V+in) including predetermined samples with no contribution of said pseudorandom sequence (γ-ts); - a prediction block (10) to produce a digital estimation (Dout) of said input signal (Vin).

Abstract translation: 多级ADC（1）用于将多个输入信号（VIn）的多步循环的模拟样本（V] n）转换为数字代码（Dout），每个周期分解至少一位数字代码（Dout），转换器 1）包括： - 要与所述模拟样本求和的伪随机序列（Y'ts）的生成块（3），获得模拟样本的第二序列（V + in）; - 具有可控数字增益（g）的转换装置（5），接收第二序列（V + in）并输出所述数字码（Dout）的位; - 用于通过循环增益（GLoop）执行所述多级转换循环的反馈回路（2,6,7,8）; - 将数字增益（g）与环路增益（GLoop）匹配的数字校准块（9）; 所述第二序列（V + in）包括没有所述伪随机序列（α-ts）的贡献的预定样本; - 产生所述输入信号（Vin）的数字估计（Dout）的预测块（10）。

公开(公告)号：WO2007032032A1

公开(公告)日：2007-03-22

申请号：PCT/IT2005/000529

申请日：2005-09-16

Applicant: STMICROELECTRONICS S.R.L. ,  MURARI, Bruno ,  RICOTTI, Giulio ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo

Inventor： MURARI, Bruno ,  RICOTTI, Giulio ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo

IPC: G01L1/02 ,  G01L9/00

CPC classification number: G01L9/0054 ,  G01L1/02 ,  G01L5/225 ,  G01L9/0045 ,  G01L9/0089 ,  G01L19/0645 ,  G01L19/146

Abstract: In a pressure sensor (35) , a pressure-sensor element (10) has a monolithic body (12) of semiconductor material, and a first main face (12a) and a second main face (12b) acting on which is a stress resulting from a pressure (P) the value of which is to be determined; and a package (36) encloses the pressure­sensor element (10) . The package (36) has an inner chamber (37) containing liquid material (38), and the -ores sure-sensor element (10) is arranged within the inner chamber (37) in such a manner that the first and second main faces (12a, 12b) are both in contact with the liquid material (38). In particular, the liquid material is a silicone gel.

Abstract translation: 在压力传感器（35）中，压力传感器元件（10）具有半导体材料的整体（12），并且作用于其上的应力产生的第一主面（12a）和第二主面（12b） 从压力（P）来确定其值; 并且包装（36）包围所述压力传感器元件（10）。 包装（36）具有容纳液体材料（38）的内部室（37），并且 - 确定传感器元件（10）以这样的方式设置在内部室（37）内，使得第一和第二主要面 （12a，12b）都与液体材料（38）接触。 特别地，液体材料是硅胶。

公开(公告)号：WO2007031536A1

公开(公告)日：2007-03-22

申请号：PCT/EP2006/066316

申请日：2006-09-13

Applicant: STMICROELECTRONICS S.R.L. ,  KARPOV, Ilya ,  KIM, Yudong ,  JIN, Ming ,  TEEGAPURAM, Shyam Prasad ,  LEE, Jinwook

Inventor： KARPOV, Ilya ,  KIM, Yudong ,  JIN, Ming ,  TEEGAPURAM, Shyam Prasad ,  LEE, Jinwook

IPC: H01L27/24

CPC classification number: H01L45/16 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126

Abstract: A phase change memory formed by a plurality of phase change memory devices having a chalcogenide memory region (28) extending over an own heater (26). The heaters (26) have all a relatively uniform height. The height uniformity is achieved by forming the heaters within pores in an insulator that includes an etch stop layer (18) and a sacrificial layer (24). The sacrificial layer is removed through an etching process such as chemical mechanical planarization. Since the etch stop layer may be formed in a repeatable way and is common across all the devices on a wafer, considerable uniformity is achieved in heater height. Heater height uniformity results in more uniformity in programmed memory characteristics.

Abstract translation: 一种由具有在自身加热器（26）上延伸的硫族化物存储区域（28）的多个相变存储器件形成的相变存储器。 加热器（26）具有相对均匀的高度。 通过在包括蚀刻停止层（18）和牺牲层（24）的绝缘体的孔内形成加热器来实现高度均匀性。 通过诸如化学机械平面化的蚀刻工艺去除牺牲层。 由于蚀刻停止层可以以可重复的方式形成，并且在晶片上的所有器件上是共同的，所以在加热器高度方面实现了相当大的均匀性。 加热器高度均匀性导致编程存储器特性更均匀。