公开(公告)号：US20190171819A1

公开(公告)日：2019-06-06

申请号：US16175699

申请日：2018-10-30

Applicant: STMicroelectronics, Inc.

Inventor： Maurizio Gentili ,  Massimo Panzica

IPC: G06F21/57 ,  G06F12/14

Abstract: Electronic computing devices provide a method to update firmware. The method includes receiving a firmware image at an electronic device, the electronic device having a processor and a memory arranged to store instructions executed by the processor. In the electronic device, a unique device identifier is retrieved and a random number is generated. The generated random number is securely stored. The random number and a representation of the unique device identifier are computationally combined to create a device-binding value, and an address-offset is generated from the device-binding value. The firmware image is stored in the memory at the address-offset.

公开(公告)号：US10304815B2

公开(公告)日：2019-05-28

申请号：US15802541

申请日：2017-11-03

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US20190149081A1

公开(公告)日：2019-05-16

申请号：US16250055

申请日：2019-01-17

Applicant: STMicroelectronics, Inc.

Inventor： Cheng PENG ,  Robert KRYSIAK

IPC: H02P29/60 ,  H02P27/08 ,  H02P29/024

Abstract: A system in package encloses a sensor and motor driver circuit. In an implementation, the sensor is an integrated circuit micro-electro-mechanical-systems (MEMS) sensor and the driver circuit is a motor driver circuit. Non-motor winding data information is sensed by the MEMS sensor and processed for the purpose of characterizing known fault patterns for motors; characterizing normal operation of the motor; and evaluating continued operation of the motor to detect abnormal motor behavior and instances of motor fault. The motor is driven using PWM control and the information output by the MEMS sensor is sampled at sampling times having a fixed timing relationship relative to the PWM control signals.

公开(公告)号：US20190141789A1

公开(公告)日：2019-05-09

申请号：US16233926

申请日：2018-12-27

Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD ,  STMICROELECTRONICS, INC.

Inventor： Fuchao WANG ,  Olivier LENEEL ,  Ravi SHANKAR

IPC: H05B3/00 ,  H05B3/34 ,  H01L23/34 ,  H05B3/02 ,  H05B3/06 ,  H05B1/02 ,  H05B3/12

Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.

公开(公告)号：US10283418B2

公开(公告)日：2019-05-07

申请号：US16027889

申请日：2018-07-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  James Kuss ,  Nicolas Loubet ,  Junli Wang

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L27/092 ,  H01L27/12 ,  H01L29/161

Abstract: A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer; removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids; exposing the silicon layer of the fin structures in the first region and a second regions; and thermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.

公开(公告)号：US10261128B2

公开(公告)日：2019-04-16

申请号：US15466001

申请日：2017-03-22

Applicant: STMicroelectronics, Inc.

Inventor： Pramod Kumar ,  Vinay Kumar

IPC: G01R31/317 ,  G01R31/3177

Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a scan chain configured to receive test pattern data and to shift the test pattern data to the device under test, and being clocked by a reference clock, and a clock circuit configured to operate in either a clock generation mode or a frequency determination mode. The clock circuit, when in the clock generation mode and when the test circuit is in a normal mode of operation, is configured to pass a first clock signal to the device under test. The clock circuit, when in the clock generation mode and when the test circuit is in a test mode of operation, is configured to pass the reference clock to the device under test. The clock circuit, when in the frequency determination mode, counts a frequency of the first clock signal.

公开(公告)号：US10256751B2

公开(公告)日：2019-04-09

申请号：US15065617

申请日：2016-03-09

Applicant: STMicroelectronics, Inc.

Inventor： Frederic Bonvin

IPC: H02P6/14 ,  H02P3/12 ,  G11B19/20 ,  H02M7/5388 ,  H02P3/22 ,  H02P6/08

Abstract: A drive circuit having asymmetrical drivers. In an embodiment, a brushless DC motor may be driven by a drive circuit having three high-side MOSFETs and three low-side MOSFETs. A driver controller turns the MOSFETs on and off according to a drive algorithm such that phase currents are injected into motor coils to be driven. The high-side MOSFETs may be sized differently than the low-side MOSFETs. As such, when a MacDonald waveform (or similar drive algorithm) is used to drive the phases of the motor, less power may be required during disk spin-up because the MOSFETs that are on more (e.g., the low-side MOSFETs with a MacDonald waveform) may be sized larger than the MOSFETs that are on less (e.g., the high-side MOSFETs). In this manner, less power is dissipated in the larger size MOSFETs that are on more than the others.

公开(公告)号：US10256351B2

公开(公告)日：2019-04-09

申请号：US15723149

申请日：2017-10-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/00 ,  H01L29/788 ,  H01L21/02

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

公开(公告)号：US10249568B2

公开(公告)日：2019-04-02

申请号：US15967336

申请日：2018-04-30

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/06 ,  H01L27/08

Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

公开(公告)号：US20190097303A1

公开(公告)日：2019-03-28

申请号：US16123908

申请日：2018-09-06

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Rizzo ,  Christophe Henri Ricard

IPC: H01Q1/22 ,  H04B5/00 ,  G01V3/10

Abstract: A method and apparatus for performing a low-power presence check are provided. In the method and apparatus, a controller detects a presence of a tag by at least causing the antenna to generate a magnetic field over a first time period for detecting the tag, measuring an antenna voltage over a second time period, causing the antenna to cease generating a magnetic field over a third time period longer than the first time period and comparing the antenna voltage to an antenna reference voltage to determine whether the tag is present. The controller detects the presence of the tag in response to receiving a command from a host device for performing the low-power presence check. The command may be a one-time command for every presence check stage or a command that is repeatedly received each time the controller detects the presence of the tag.