公开(公告)号：US20180175202A1

公开(公告)日：2018-06-21

申请号：US15890880

申请日：2018-02-07

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/417 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/1033 ,  H01L21/30621 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

公开(公告)号：US20180158945A1

公开(公告)日：2018-06-07

申请号：US15884843

申请日：2018-01-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7849 ,  H01L2029/7858

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

公开(公告)号：US20180144952A1

公开(公告)日：2018-05-24

申请号：US15876046

申请日：2018-01-19

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo ,  Godfrey Dimayuga

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: One or more embodiments are directed to semiconductor packages with one or more cantilever pads and methods of making same. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.

公开(公告)号：US09980219B2

公开(公告)日：2018-05-22

申请号：US15808592

申请日：2017-11-09

Applicant: STMICROELECTRONICS, INC.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W52/02 ,  H04W8/22 ,  H04W88/02 ,  H04W88/08 ,  H04W84/12

CPC classification number: H04W52/0209 ,  H04W8/22 ,  H04W52/0206 ,  H04W52/0216 ,  H04W52/0222 ,  H04W52/0229 ,  H04W84/12 ,  H04W88/02 ,  H04W88/08 ,  Y02D70/00 ,  Y02D70/142

Abstract: A IEEE 802.11 Wireless Local Area Network (WLAN) system of an access point (AP) and one or more stations (STAs) reduces power consumption and increases battery life of power efficient low power STAs by decreasing the amount of time that a power efficient low power STA remains in an awake state. After indicating power efficient low power operation during association with an AP supporting such operation, the power efficient low power STA may enter the doze state from the time that the power efficient low power STA sends a PS-Poll until the power efficient low power STA receives the buffered DATA frame from the AP. While implementing the power efficient PS-Poll method, the AP can send the buffered DATA frame to the STA SIFS after the AP sends an ACK to the received PS-Poll from the STA.

公开(公告)号：US09972558B1

公开(公告)日：2018-05-15

申请号：US15479068

申请日：2017-04-04

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo ,  Tito Mangaoang

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/27 ,  H01L24/32 ,  H01L24/46 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/92125

Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.

公开(公告)号：US09968700B2

公开(公告)日：2018-05-15

申请号：US14975200

申请日：2015-12-18

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Simon Dodd ,  Joseph Edward Scheffelin ,  Dave S. Hunt ,  Timothy James Hoekstra ,  Faiz Sherman ,  Stephan Gary Bush

IPC: A61L9/03 ,  B05B17/06 ,  A61L2/00 ,  A61L9/00

CPC classification number: A61L9/03 ,  A61L2/00 ,  A61L9/00 ,  B05B17/0684

Abstract: One or more embodiments are directed to a microfluidic delivery system that dispenses a fluid. The microfluidic delivery system may be provided in a variety of orientations. In one embodiment, the microfluidic delivery system is vertical so that fluid being expelled opposes gravity. In another embodiment, the microfluidic delivery system is orientated sideways so that fluid being expelled has a horizontal component. In yet another embodiment, the microfluidic delivery system faces downward.

公开(公告)号：US09953933B1

公开(公告)日：2018-04-24

申请号：US15474904

申请日：2017-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Aaron Cadag ,  Rennier Rodriguez ,  Ela Mia Cadag

IPC: H01L23/552 ,  H01L23/00 ,  B32B7/12 ,  H01L21/78 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/552 ,  B32B7/12 ,  B32B2457/14 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48229 ,  H01L2224/48992 ,  H01L2924/15311 ,  H01L2924/3025

Abstract: A semiconductor package includes a substrate, a die, an insulating die attach film, a dummy die, a conductive layer, and an electrically conductive molding compound or encapsulant. The first surface of the substrate includes a plurality of internal leads, and the second surface of the substrate includes a plurality of external electrically conductive pads and an electrically conductive ground terminal. A non-conductive flow over wire die attach film is placed to surround and encase the die. The dummy die overlies the die and a conductive layer overlies the dummy die. The electrically conductive molding compound is formed to encase the various components of the semiconductor device. The electrically conductive molding compound is electrically coupled to the electrically conductive ground terminal and the conductive layer forming an EMI shield for the die in the package.

公开(公告)号：US09948981B2

公开(公告)日：2018-04-17

申请号：US15078825

申请日：2016-03-23

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Neil Robertson ,  Jean-Yves Couet

IPC: H04N21/442 ,  H04N21/437 ,  H04N21/61 ,  H04N7/173

CPC classification number: H04N21/44245 ,  H04N7/17309 ,  H04N21/437 ,  H04N21/6118 ,  H04N21/6168 ,  H04N21/6193

Abstract: An upstream signal capture device includes a signal capture circuit having a first port and a second port. The first port of the signal capture circuit is arranged for coupling to a diplexer. The upstream signal capture device also includes an amplifier having a first port and a second port, the first port of the amplifier coupled to the second port of the signal capture circuit, and an analog-to-digital converter (ADC) having a first port and a second port, the first port of the ADC coupled to the second port of the amplifier. The upstream signal capture device further includes a digital threshold detector having an input and output, the input of the digital threshold detector coupled to the second port of the analog-to-digital converter, and a memory configured to capture samples of the upstream signal. When using the upstream signal capture device to capture an upstream signal, a portion of an upstream signal is diverted into an analog-to-digital converter (ADC). A portion of the upstream signal is converted into a digital signal, and when the digital signal exceeds a threshold, the signal is captured in a memory.

公开(公告)号：US09947772B2

公开(公告)日：2018-04-17

申请号：US14231466

申请日：2014-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/7845 ,  H01L29/785

Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.

公开(公告)号：US09939481B2

公开(公告)日：2018-04-10

申请号：US15603181

申请日：2017-05-23

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics S.r.l.

Inventor： Oleg Logvinov ,  Roberto Cappelletti ,  Mauro Conti

IPC: H01H31/12 ,  G01R31/02 ,  H04B3/54

CPC classification number: G01R31/024 ,  H04B3/54 ,  H04B2203/5458 ,  H04B2203/5495

Abstract: Embodiments of the present disclosure include a method of operating an arc fault detection system, an arc fault detection system, and a system. An embodiment is a method of operating an arc fault detection system coupled to a power line, the method including determining one or more arc fault detection windows in power line signals on the power line, the power line signals comprising a communication signal and an alternating current (AC) power signal. The method further includes receiving the power line signals from the power line during the one or more arc fault detection windows, and performing arc fault detection processing on the received power line signals.