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    Large multiplier for programmable logic device
    32.
    发明专利
    Large multiplier for programmable logic device 有权
    用于可编程逻辑器件的大型多路复用器

    公开(公告)号：JP2012248208A

    公开(公告)日：2012-12-13

    申请号：JP2012172915

    申请日：2012-08-03

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： LANGHAMMER MARTIN ,  THARMALINGAM KUMARA

    IPC: G06F7/52

    CPC classification number: G06F7/52 ,  G06F7/5324

    Abstract: PROBLEM TO BE SOLVED: To provide special processing blocks for a programmable logic device (PLD) with logic for reducing or eliminating dependence on a universal programmable resource of the PLD by facilitating execution of a larger multiplication than the one to be executed in a single block.SOLUTION: A plurality of special processing blocks in a PLD including multipliers, and circuitry for an adder which adds results of the multipliers are constituted as larger multipliers by adding selectable circuitry for shifting the results of the multipliers before addition to the special processing blocks. In one embodiment, this fact allows that all except the final addition are performed in the special processing blocks, and the final addition is performed in programmable logic. In another embodiment, circuitry of additional compression and addition allows that even the final addition is performed in the special processing blocks.

    Abstract translation: 要解决的问题：为可编程逻辑器件（PLD）提供特殊的处理块，其具有用于通过促进执行比要执行的PLD更大的乘法来减少或消除对PLD的通用可编程资源的依赖性的逻辑 单块。 解决方案：包括乘法器的PLD中的多个特殊处理块和用于加法乘法器的结果的加法器的电路被构成为较大的乘法器，通过增加用于在乘法器的结果之前移位乘法器的特定处理的可选择电路 块。 在一个实施例中，这个事实允许在特殊处理块中执行除了最终加法之外的所有其它事件，并且以可编程逻辑执行最后的加法。 在另一个实施例中，附加压缩和附加的电路允许即使在特殊处理块中执行最终添加。 版权所有（C）2013，JPO＆INPIT

    Process/design methodology to enable high performance logic and analog circuits using single process
    36.
    发明专利
    Process/design methodology to enable high performance logic and analog circuits using single process 有权
    使用单一过程实现高性能逻辑和模拟电路的过程/设计方法

    公开(公告)号：JP2012119701A

    公开(公告)日：2012-06-21

    申请号：JP2012003044

    申请日：2012-01-11

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： QI XIANG ,  ALBERT RATNAKUMAR ,  JEFFREY XIAOCHI TANG ,  WEICH DIN

    IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H03F3/343

    CPC classification number: G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

    Abstract: PROBLEM TO BE SOLVED: To provide a method and apparatus for improving analog circuits performance on a mixed-signal process.SOLUTION: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit including plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source, and the body terminal of the PMOS transistors are coupled to a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

    Abstract translation: 要解决的问题：提供一种用于在混合信号处理中提高模拟电路性能的方法和装置。 提出了一种使用正向偏置电路设计和改进的混合信号处理来提高模拟电路性能的方法。 定义了包括多个NMOS和PMOS晶体管的电路。 NMOS晶体管的主体端子耦合到第一电压源，并且PMOS晶体管的主体端子耦合到第二电压源。 通过将第一电压源施加到每个选定的NMOS晶体管的主体端子并将第二电压源施加到每个选择的PMOS晶体管的主体端子来选择性地偏置电路中的晶体管。 在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的主体端子提供正向和反向偏置。 版权所有（C）2012，JPO＆INPIT

    Offset cancellation for continuous-time circuit
    37.
    发明专利
    Offset cancellation for continuous-time circuit 有权
    用于连续电路的偏移消除

    公开(公告)号：JP2012114914A

    公开(公告)日：2012-06-14

    申请号：JP2011255026

    申请日：2011-11-22

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： SYRIAM NARAYAN ,  SU XIAOYAN ,  SURGEY SHUMARAYEV

    IPC: H03F3/34

    CPC classification number: H03F1/30 ,  H03F3/45197 ,  H03F3/45973 ,  H03F2200/375 ,  H03F2200/405 ,  H03F2203/45354 ,  H03F2203/45374

    Abstract: PROBLEM TO BE SOLVED: To improve equalizers and other continuous-time circuits for high-speed serial interfaces and other applications.SOLUTION: The circuit includes: a multistage amplifier chain including a first amplifier stage and a last amplifier stage in the chain; and an offset cancellation loop configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage.

    Abstract translation: 要解决的问题：为了提高高速串行接口和其他应用的均衡器和其他连续时间电路。 解决方案：该电路包括：多级放大器链，包括链中的第一放大级和最后的放大级; 以及偏移消除环路，被配置为接收最后的放大器级的输出，并向第一放大器级提供偏移校正电压信号。 版权所有（C）2012，JPO＆INPIT

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