公开(公告)号：EP0441787B1

公开(公告)日：1994-12-07

申请号：EP89908984.1

申请日：1989-08-09

Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap ,  ALCATEL N.V.

Inventor： HENRION, Michel, André, Robert

IPC: H04L12/56

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/608

Abstract: The switching element is used for transferring, between X inputs (I1 - IX) and Y outputs (O1 - OY), cells divided into subcells of which only the first contains information about the destination output(s) of the cell. This switching element includes: a buffer memory (BM) with a plurality (C) of memory locations each having an address (K); and a memory management means (BMMU) for providing (FMLMC) addresses of free memory locations for storing the subcells therein, and for storing (BQ1 - BQY, SLM), under the form of linked lists, the memory location addresses used by the subcells, each list being associated to a distinct cell. The method is adapted to process variable length cells divided into subcells each containing a header (SCH) to distinguish a first/last subcell (FSC/LSC) of a cell from other subcells (ISC, LSC). Use is made of a subcell logic (SL) to detect the succession in either order of a subcell pertaining to a cell and of either a first/last subcell (FSC/LSC) of another cell or an idle subcell so as to identify the last/first subcell (LSC/FSC) of a cell.

公开(公告)号：EP0446493B1

公开(公告)日：1994-11-30

申请号：EP90200594.1

申请日：1990-03-14

Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

Inventor： Henrion, Michel André Robert

IPC: H04L12/56

CPC classification number: H04L45/00 ,  H04L12/18 ,  H04L12/5601 ,  H04L45/16 ,  H04L49/106 ,  H04L49/256 ,  H04L49/309

公开(公告)号：EP0430955B1

公开(公告)日：1994-06-01

申请号：EP89907717.6

申请日：1989-06-23

Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap ,  ALCATEL N.V.

Inventor： MESTDAGH, Denis, Julien, Gilles ,  VAN ENGELSHOVEN, Robertus, Josephus ,  PAUWELS, Bart, Joseph, Gerard

IPC: H04L12/28 ,  H04L12/40

CPC classification number: H04L12/28

Abstract: This system includes a main station (MS) and a plurality of substations (SX/SZ) which include each a transceiver and are all connected in parallel to first (UL) and second (DL) unidirectional links on which recurrent first and second cells of fixed length are transmitted in opposite direction. Each of these cells contains a plurality of signalling channels smaller than the number of substations. When a substation has to transmit data it starts an allocation procedure wherein the substation cooperates with the main station and by which a channel is allocated to it. Afterwards prior to transmitting the data the substation transmits a request signal in the allocated channel and starts transmission after having received from the main station a grant signal in the homologous signalling channel of a second cell. De-allocation of a channel occurs as soon as the latter is no longer needed.

Abstract translation: 该系统包括一个主站（MS）和多个分站（SX / SZ），它们各自包括一个收发信机，并且全部与第一（UL）和第二（DL）单向链路并联连接，第一和第二 固定长度以相反的方向传输。 每个这些小区包含多个小于分站数量的信令信道。 当变电站必须传输数据时，它开始一个分配过程，其中变电站与主站合作并且通过该分配信道为其分配信道。 之后，在发送数据之前，变电站在分配的信道中发送请求信号，并且在从主站接收到第二小区的同源信令信道中的授权信号之后开始发送。 一旦不再需要后者，就会发生信道解除分配。

公开(公告)号：EP0322025B1

公开(公告)日：1994-03-30

申请号：EP88202851.7

申请日：1988-12-13

Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

Inventor： Verbert, Robert Eugène Philomena ,  Van Simaeys, François

IPC: H04L25/08 ,  H04Q11/04 ,  H03K17/687

CPC classification number: H04L25/02

公开(公告)号：EP0424390B1

公开(公告)日：1993-12-29

申请号：EP89904035.6

申请日：1989-04-01

Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY NAAMLOZE VENNOOTSCHAP

Inventor： WILLOCX, Eddie, Louis, Marie

IPC: G01R19/00 ,  H03K5/24 ,  H03K17/693

CPC classification number: H03K17/693 ,  G01R19/0038 ,  H03K5/2481

Abstract: A voltage selector uses a comparator (COMP) in order to clamp the potential (VSUB) of a p-doped substrate of a telecommunication Subscriber Line Integrated Circuit to the most negative voltage appearing at two input terminals (V1/2), one being supplied with the battery voltage and the other with a synthesized voltage, both varying within a relatively wide range with either one being able to be more negative than the other. With V1/2 connected to VSUB through respective DMOS transistors (N1/2), V1/2 also constitute the inputs of COMP whose outputs (C1/2) are connected to the gates of the DMOS transistors. The comparator is so designed as to allow a fast change-over of the opposite conductivity states of N1 and N2 whenever there is an inversion in the relative magnitudes of the V1 and V2 voltages, the voltage drop over a conductive N1/2 transistor being much lower than in the case of clamping diodes.

公开(公告)号：EP0535272A1

公开(公告)日：1993-04-07

申请号：EP91202570.7

申请日：1991-10-02

Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

Inventor： Van der Putten, Frank Octaaf ,  Deloddere, Chris Frans Philippe

IPC: H04N7/13

CPC classification number: H04N19/423 ,  H04N19/124 ,  H04N19/132 ,  H04N19/60 ,  H04N19/61 ,  H04N19/619 ,  H04N19/82

Abstract: The encoder arrangement, apart from the generally used circuitry consisting of a transform circuit (DCT), a quantizer (Q) and dequantizer (Qi) circuit, a packetizer/encoder (VLC), a substraction circuit (SUB) to determine the difference between a current and a previous image block, an adder circuit (AD) to add the above difference to a previous image block and a memory module (M) to memorize the mentioned previous image block, includes a selection circuit (SE) to select only part of the image block for memorization and a supplementing circuit (SU) to supplement the thus partly memorized image block with zeros to obtain a complete previous image block. In this way the memory capacity for memorization of the image blocks can be reduced.

Abstract translation: 除了由变换电路（DCT），量化器（Q）和去量化器（Qi）电路组成的一般使用的电路之外，编码器装置，分组器/编码器（VLC），减法电路（SUB） 当前和先前的图像块，将上述差值加到先前图像块的加法器电路（AD）和用于存储所述先前图像块的存储器模块（M）包括选择电路（SE），以仅选择部分 用于存储的图像块和补充电路（SU），用零补充这样部分存储的图像块，以获得完整的先前图像块。 以这种方式，可以减少用于存储图像块的存储器容量。

公开(公告)号：EP0143473B1

公开(公告)日：1992-05-06

申请号：EP84201211.4

申请日：1984-08-22

Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap ,  ALCATEL N.V.

Inventor： Remmerie, Guido ,  Van den Bossche, Luc J.L.

IPC: H03K17/56 ,  H03K17/08 ,  H02H9/02 ,  H04M1/31

CPC classification number: H03K17/6872 ,  H03K17/6874 ,  H03K17/73 ,  H04M3/005 ,  H04M19/02 ,  Y02D70/122 ,  Y02D70/21

Abstract: High voltage electronic contacts (S, S min ) and associated devices including TRIMOS (MOS TRlacs) devices connected in anti-parallel fashion between two terminals (S1/S min 2, S2/S min 1). Each electronic contact (S, S min ) is controlled via a control terminal (S4) by two auxiliary electronic contacts (NA, NB) each able to establish a low or high impedance between the control terminal (S4) and one of the two other terminals (S1/S min 2, S2/S min 1), the impedance conditions of these auxiliary contacts (NA, NB) being opposed. A power protection circuit associated to the TRIMOS device allows the flow of a relatively high current through the electronic contacts (S, S min ) for the lower voltage range across it, and minimizes the power dissipation in the contacts in the higher voltage range, i.e. when abnormally high signals are applied to the contact.

Abstract translation: 包括在两个端子之间以反并联方式连接的TRIMOS（MOS TRlacs）器件的高压电子触点（S，S min）和相关器件（S1 / S min 2，S2 / S min 1）。 每个电子触点（S，S min）通过控制端子（S4）由两个辅助电子触点（NA，NB）控制，每个辅助电子触点（NA，NB）能够在控制端子（S4）和其他两个之间建立低阻抗或高阻抗 端子（S1 / S min 2，S2 / S min 1），这些辅助触点（NA，NB）的阻抗条件相反。 与TRIMOS器件相关联的电源保护电路允许通过电子触点（S，S min）的相对较高的电流流过跨越其的较低电压范围，并且在较高电压范围内使触点中的功率消耗最小化，即 当异常高的信号被施加到触点时。

公开(公告)号：EP0458798A1

公开(公告)日：1991-12-04

申请号：EP90901779.0

申请日：1989-12-19

Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap ,  Alcatel N.V.

Inventor： DE GROOTE, Jan, Lieven, Bert

IPC: G05F3 ,  G06F13 ,  H02H9

CPC classification number: G06F13/4081 ,  H02H9/004

Abstract: Circuit de commande de courant pour carte de circuits portant un circuit parallèle comprenant un condensateur d'entrée (Cb) monté en dérivation à l'aide d'un circuit électronique (CI) constitué par des dispositifs à MOS complémentaires ne dissipant pas de puissance pour autant qu'aucun signal d'horloge (CK) ne leur soit appliqué. Ce circuit de commande limite les variations de tension dans d'autres circuits parallèles se trouvant sur d'autres cartes de circuits déjà couplées à une alimentation en puissance (PS), c'est-à-dire à l'aide de condensateurs d'entrée chargés, lorsque la carte de circuit de l'invention est récemment couplée à cette alimentation en puissance ou à cette source de puissance. On obtient cet agencement, premièrement, par intercouplage du circuit parallèle et de la source par l'intermédiaire d'une résistance et tout en empêchant l'application du signal d'horloge (CK) au circuit électronique (CI) et par application de ce signal d'horloge au circuit électronique (CI) pendant une durée (Th) augmentant graduellement, une fois la résistance court-circuitée.

公开(公告)号：EP0451372A1

公开(公告)日：1991-10-16

申请号：EP90200923.2

申请日：1990-04-13

Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

Inventor： Sevenhans, Joannes Mathilda Josephus

IPC: H03C1/54

CPC classification number: H03C1/545 ,  H03C2200/0012 ,  H03C2200/0025 ,  H03C2200/0079

Abstract: Modulator circuit (MOD) with a modulator proper and a correction signal generator. The modulator proper comprises the cascade connection of an amplifier (T11, T21, CS11, T12, T22, CS12) and a first switching circuit (R11, T31, T51, R12, T32, T52), whilst the generator comprises the cascade connection of the same amplifier and a second switching circuit (R21, T61, T42, R22, T62, T41) having a correction output (P11, P12) coupled to a feedback input (P21, P22) of the amplifier via a feedback circuit (T71, R31, CS21, T72, R32, CS22). The amplifier and the switching circuits are controlled by a modulating signal and a carrier signal respectively and the first and second switching circuits provide a modulated output signal and a correction signal substantially equal to the envelope of the modulated output signal and used to decrease the modulator distortion.

Abstract translation: 具有调制器的调制器电路（MOD）和校正信号发生器。 调制器本身包括放大器（T11，T21，CS11，T12，T22，CS12）和第一开关电路（R11，T31，T51，R12，T32，T52）的级联连接，而发电机包括级联 具有通过反馈电路（T71，...）耦合到放大器的反馈输入（P21，P22）的校正输出（P11，P12）的相同放大器和第二开关电路（R21，T61，T42，R22，T62，T41） R31，CS21，T72，R32，CS22）。 放大器和开关电路分别由调制信号和载波信号控制，第一和第二开关电路提供调制输出信号和基本上等于调制输出信号的包络的校正信号，并用于减小调制器失真 。

公开(公告)号：EP0154371B1

公开(公告)日：1991-07-03

申请号：EP85200208.8

申请日：1985-02-19

Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap ,  Alcatel N.V.

Inventor： Van Simaeys, Françoise Catherine Gabrielle ,  Guebels Pierre-Paul François Maurice

IPC: H04Q11/04

CPC classification number: H04Q11/04 ,  H04Q11/0407