公开(公告)号：WO2010138308A1

公开(公告)日：2010-12-02

申请号：PCT/US2010/034550

申请日：2010-05-12

Applicant: GLOBALFOUNDRIES INC. ,  MATHUR, Kaveri ,  BULLER, James, F. ,  KURZ, Andreas

Inventor： MATHUR, Kaveri ,  BULLER, James, F. ,  KURZ, Andreas

IPC: H01L21/329 ,  H01L29/8605 ,  H01L27/07

CPC classification number: H01L29/8605 ,  H01L27/0738 ,  H01L27/0802 ,  H01L29/66166

Abstract: Semiconductor devices are formed with reduced variability between close proximity resistors, improved end resistances, and reduced random dopant mismatch. Embodiments include ion implanting a dopant, such as B, at a relatively high dosage, e.g. about 4 to about 6keV, and at a relatively low implant energy, e.g., about 1.5 to about 2E15/cm 2 .

Abstract translation: 半导体器件形成在近距离电阻之间具有降低的变异性，改善的端电阻和减少的随机掺杂物失配。 实施例包括以相当高的剂量例如离子注入掺杂剂，例如B。 约4至约6keV，并且在相对较低的注入能量下，例如约1.5至约2E15 / cm 2。

公开(公告)号：WO2010132277A1

公开(公告)日：2010-11-18

申请号：PCT/US2010/033948

申请日：2010-05-07

Applicant: GLOBALFOUNDRIES INC. ,  FEUSTEL, Frank ,  LETZ, Tobias ,  PREUSSE, Axel

Inventor： FEUSTEL, Frank ,  LETZ, Tobias ,  PREUSSE, Axel

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76849 ,  H01L21/76867 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In sophisticated semiconductor devices, the electromigration performance of copper metal lines at the top interface thereof may be enhanced by forming a copper alloy (132C) that is locally restricted to the interface (132S). To this end, an appropriate alloy-forming species, such as aluminum, may be provided on the basis of a non-masked deposition process and may be subsequently removed by a non-masked etch process, wherein the characteristic of the resulting alloy may be adjusted during an intermediate heat treatment.

Abstract translation: 在复杂的半导体器件中，通过形成局部限于界面（132S）的铜合金（132C）可以提高铜金属线在其顶部界面处的电迁移性能。 为此，可以在非掩蔽沉积工艺的基础上提供合适的合金形成物质，例如铝，然后通过非掩模蚀刻工艺除去，其中所得合金的特征可以是 在中间热处理期间调整。

公开(公告)号：WO2010085512A1

公开(公告)日：2010-07-29

申请号：PCT/US2010/021555

申请日：2010-01-21

Applicant: GLOBALFOUNDRIES INC. ,  HUGHES, William, A. ,  BONDALAPATI, Kiran, K. ,  KALYANASUNDHARAM, Vydhyanathan ,  LEPAK, Kevin, M. ,  SANDER, Benjamin, T.

Inventor： HUGHES, William, A. ,  BONDALAPATI, Kiran, K. ,  KALYANASUNDHARAM, Vydhyanathan ,  LEPAK, Kevin, M. ,  SANDER, Benjamin, T.

IPC: G06F12/08 ,  G06F1/32

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F12/0808 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D50/20

Abstract: A data processing device [100] is disclosed that includes multiple processing cores [110, 120, 130], where each core is associated with a corresponding cache [112, 122, 132]. When a processing core is placed into a first sleep mode [220], the data processing device initiates a first phase [220]. If any cache probes are received at the processing core during the first phase, the cache probes are serviced [230]. At the end of the first phase, the cache corresponding to the processing core is flushed [240], and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.

Abstract translation: 公开了一种数据处理设备[100]，其包括多个处理核心[110,120,130]，其中每个核心与相应的高速缓存[112,122,132]相关联。 当处理核心被置于第一睡眠模式[220]时，数据处理设备启动第一阶段[220]。 如果在第一阶段期间在处理核心处接收到任何高速缓存探测器，则对高速缓存探测器进行服务[230]。 在第一阶段结束时，与处理核心相对应的缓存被刷新[240]，并且后续的缓存探测器不在高速缓存处理服务。 因为它不服务后续的缓存探测器，因此处理核心可以进入另一个睡眠模式，从而允许数据处理设备节省额外的功率。

公开(公告)号：WO2010036347A1

公开(公告)日：2010-04-01

申请号：PCT/US2009/005308

申请日：2009-09-23

Applicant: GLOBALFOUNDRIES INC. ,  KOSONOCKY, Stephen, V. ,  NAFFZIGER, Samuel, D. ,  SATHE, Visvesh, S.

Inventor： KOSONOCKY, Stephen, V. ,  NAFFZIGER, Samuel, D. ,  SATHE, Visvesh, S.

IPC: H01L25/18 ,  G06F1/26 ,  G06F1/18 ,  H05K1/14

CPC classification number: H01L25/16 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0262 ,  H05K2201/10378 ,  Y10T307/406 ,  H01L2224/0401

Abstract: A device that includes an electronic device referred to as an integrated circuit interposer (110, 310, 810, 910) is disclosed. The integrated circuit includes a voltage regulator module (140, 340, 600, 700, 940). The interposer is attached to an electronic device (120, 850, 950), such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer (110, 210, 810, 910) can also conduct signaling between the attached electronic device (120, 850, 950) and another electronic device. The voltage regulator module (140, 340, 600, 700, 940) at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device (120, 850, 950). Generation of the voltage reference signal by the integrated circuit interposer (110, 310, 810, 910) can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device (120, 850, 950).

Abstract translation: 公开了一种包括被称为集成电路插入器（110,310,810,910）的电子设备的设备。 集成电路包括电压调节器模块（140,340,600,700,904）。 插入器附接到诸如另一集成电路的电子设备（120,850,950），并且便于对电子设备的电力的控制和分配。 集成电路插入器（110,210,810,910）还可以在所连接的电子设备（120,850,950）和另一个电子设备之间进行信令。 集成电路插入器处的电压调节器模块（140,340,600,700,940）可以被配置为向附接的电子设备（120,850,950）提供电压参考信号。 可以使能或禁止由集成电路插入器（110,310,810,910）产生电压参考信号，并且可以根据电子设备（120,850,910,910）的操作要求来调节电压参考信号的值， 950）。

公开(公告)号：WO2010024932A2

公开(公告)日：2010-03-04

申请号：PCT/US2009/004916

申请日：2009-08-29

Applicant: GLOBALFOUNDRIES INC. ,  MEYER, Andreas ,  LEHR, Matthias ,  KUECHENMEISTER, Frank

Inventor： MEYER, Andreas ,  LEHR, Matthias ,  KUECHENMEISTER, Frank

IPC: H01L23/29 ,  H01L21/56

CPC classification number: H01L24/85 ,  H01L21/56 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48847 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: The wire bond structure of sophisticated metallization systems, for instance based on copper, may be provided without a terminal aluminum layer and without any passivation layers for exposed copper surfaces (212S) by providing a fill material (250) after the wire bonding process in order to encapsulate at least the sensitive metal surfaces (212S) and a portion of the bond wire (230). Hence, significant cost reduction, reduced cycle times and a reduction of the required process steps may be accomplished independently from the wire bond materials used. Thus, integrated circuits requiring a sophisticated metallization system may be connected by wire bonding to the corresponding package (260) or carrier substrate with a required degree of reliability based on a corresponding fill material (250) for encapsulating at least the sensitive metal surfaces (212S).

Abstract translation: 复合金属化系统（例如基于铜）的引线接合结构可以通过在引线接合工艺之后依次提供填充材料（250）而没有端子铝层而没有任何用于暴露的铜表面（212S）的钝化层 至少封装敏感金属表面（212S）和接合线（230）的一部分。 因此，可以独立于使用的引线接合材料来实现显着的成本降低，循环时间缩短和所需工艺步骤的减少。 因此，需要复杂金属化系统的集成电路可以通过引线键合连接到基于相应的填充材料（250）的所需可靠度的相应封装（260）或载体衬底，用于至少将敏感金属表面（212S ）。

公开(公告)号：WO2017004312A1

公开(公告)日：2017-01-05

申请号：PCT/US2016/040276

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES INC. ,  HAN, Geng ,  MANSFIELD, Scott M. ,  NGUYEN-NGOC, Dominique ,  SAMUELS, Donald J ,  VISWANATHAN, Ramya

Inventor： HAN, Geng ,  MANSFIELD, Scott M. ,  NGUYEN-NGOC, Dominique ,  SAMUELS, Donald J ,  VISWANATHAN, Ramya

IPC: G03F1/70 ,  G03F7/20 ,  G06F17/50

CPC classification number: G03F1/36 ,  G03F1/144 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/0274

Abstract: A method of mask correction where two independent process models are analyzed and co-optimized simultaneously. In the method, a first lithographic process model simulation is run on a computer system that results in generating a first mask size in a first process window. Simultaneously, a second hard mask open etch process model simulation is run resulting in generating a second mask size in a second process window. Each first lithographic process model and second hard mask open etch process model simulations are analyzed in a single iterative loop and a common process window (PW) optimized between lithography and etch is obtained such that said first mask size and second mask size are centered between said common PW. Further, an etch model form is generated that accounts for differences in an etched pattern due to variation in three-dimensional photoresist profile, the model form including both optical and density terms that directly relate to an optical image.

Abstract translation: 一种掩模校正方法，其中两个独立的过程模型被同时分析和共同优化。 在该方法中，在计算机系统上运行第一光刻过程模型模拟，其导致在第一处理窗口中产生第一掩模尺寸。 同时，运行第二硬掩模开放蚀刻工艺模型模拟，导致在第二处理窗口中产生第二掩模尺寸。 在单个迭代循环中分析每个第一光刻处理模型和第二硬掩模开放蚀刻工艺模拟模拟，并且获得在光刻和蚀刻之间优化的公共工艺窗口（PW），使得所述第一掩模尺寸和第二掩模尺寸在所述 普通PW。 此外，产生蚀刻模型形式，其考虑由于三维光致抗蚀剂轮廓的变化而导致的蚀刻图案的差异，该模型形式包括与光学图像直接相关的光学和密度项。

公开(公告)号：WO2014164742A1

公开(公告)日：2014-10-09

申请号：PCT/US2014/023375

申请日：2014-03-11

Applicant: INTERMOLECULAR, INC ,  GLOBALFOUNDRIES, INC.

Inventor： LEE, Albert ,  KIM, Hoon ,  MUJUMDAR, Salil ,  HAYWOOD, Edward ,  CHOI, Kisik ,  BESSER, Paul

IPC: C23C16/04 ,  H01L21/02 ,  H01L27/06

CPC classification number: H01L29/517 ,  C23C16/32 ,  C23C16/45531 ,  H01L21/28194 ,  H01L22/14 ,  H01L22/20 ,  H01L29/4966

Abstract: ALD of Hf x A1 y C z films using hafnium chloride (HfC1 4 ) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfC1 4 pulse time allows for control of the A1 % incorporation in the Hf x A1 y C z film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the Hf x A1 y C z work function layer coupled with ALD deposited HfO 2 high-k gate dielectric layers was quantified to be mid-gap at ~4.6 eV. Thus, Hf x A1 y C z is a promising metal gate work function material allowing for the tuning of device threshold voltages (V th ) for anticipated multi-V th integrated circuit (IC) devices.

Abstract translation: 使用氯化铪（HfC14）和三甲基铝（TMA）前体的HfxAlyCz膜的ALD可与后沉积退火工艺和ALD衬垫组合以控制高k金属栅极器件中的器件特性。 HfC14脉冲时间的变化允许控制HfxAlyCz膜中的A1％掺入在10-13％的范围内。 组合工艺工具可用于各种材料堆的快速电气和材料表征。 金属氧化物半导体电容器（MOSCAP）器件中具有HfxAlyCz功函数层与ALD沉积HfO 2高k栅极电介质层耦合的有效功函数（EWF）被定义为〜4.6eV的中间隙。 因此，HfxAlyCz是一种有希望的金属栅极功能材料，允许调谐预期的多Vth集成电路（IC）器件的器件阈值电压（Vth）。

公开(公告)号：WO2013184632A1

公开(公告)日：2013-12-12

申请号：PCT/US2013/044017

申请日：2013-06-04

Applicant: INTERMOLECULAR, INC ,  GLOBALFOUNDRIES, INC

Inventor： DUONG, Anh ,  CLEMENS, Fitz ,  KARLSSON, Olov

IPC: H01L21/336

CPC classification number: C11D11/0047 ,  C11D7/04 ,  C11D7/08 ,  C11D7/265 ,  H01L21/02057 ,  H01L21/02068 ,  H01L21/28052 ,  H01L21/324 ,  H01L21/6704 ,  H01L29/4975 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66568

Abstract: A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract translation: 公开了一种在镍铂硅化过程中从半导体衬底中清除残余物的方法，包括多步残渣清洗，包括将底物暴露于王水溶液中，然后暴露于含有盐酸和过氧化氢的溶液中。 SC2溶液可以与剩余的铂残留物进一步反应，使其更易溶于水溶液，从而从基底表面溶解。

公开(公告)号：WO2011014406A1

公开(公告)日：2011-02-03

申请号：PCT/US2010/042934

申请日：2010-07-22

Applicant: GLOBALFOUNDRIES INC. ,  CHO, Hyunjin

Inventor： CHO, Hyunjin

IPC: G11C11/412 ,  H01L21/8244 ,  H01L27/11

CPC classification number: G11C11/412

Abstract: A loadless static random access memory cell (200) includes four transistors (202, 204, 206, 208). The first transistor (202) has a gate terminal (220) corresponding to a word line, a source/drain terminal (222) corresponding to a first bit line (212), and a drain/source terminal (224) corresponding to a first storage node (226). The second transistor (204) has a gate terminal (230) corresponding to the word line (210), a source/drain terminal (232) corresponding to a second bit line (214), and a drain/source terminal (234) corresponding to a second storage node (236). The third transistor (206) has a gate terminal (240) coupled to the second storage node (236), a drain terminal (242) coupled to the first storage node (226), a source terminal (244) corresponding to a reference voltage, and a body terminal (246) directly connected to the third gate terminal (240). The fourth transistor (208) has a gate terminal (250) coupled to the first storage node (226), a drain terminal (252) coupled to the second storage node (236), a source terminal (254) corresponding to the reference voltage, and a body terminal (256) directly connected to the fourth gate terminal (250).

Abstract translation: 无负载静态随机存取存储单元（200）包括四个晶体管（202,204,206,208）。 第一晶体管（202）具有对应于字线的栅极端子（220），对应于第一位线（212）的源极/漏极端子（222）和与第一晶体管对应的漏极/源极端子（224） 存储节点（226）。 第二晶体管（204）具有对应于字线（210）的栅极端子（230），对应于第二位线（214）的源极/漏极端子（232）和对应于漏极/源极端子 到第二存储节点（236）。 第三晶体管（206）具有耦合到第二存储节点（236）的栅极端子（240），耦合到第一存储节点（226）的漏极端子（242），对应于参考电压 ，以及直接连接到第三栅极端子（240）的主体端子（246）。 第四晶体管（208）具有耦合到第一存储节点（226）的栅极端子（250），耦合到第二存储节点（236）的漏极端子（252），对应于参考电压 ，以及直接连接到第四栅极端子（250）的主体端子（256）。

公开(公告)号：WO2011013091A2

公开(公告)日：2011-02-03

申请号：PCT/IB2010/053457

申请日：2010-07-29

Applicant: GLOBALFOUNDRIES INC. ,  WALTER, Axel ,  LEHR, Matthias

Inventor： WALTER, Axel ,  LEHR, Matthias

CPC classification number: H01L23/481 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/3677 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/552 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06133 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer (260), which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer (260) comprises copper-based buffer regions (265) that cover a significant portion of the overall surface, wherein a thickness of approximately 3- 10 μm may also be used. Moreover, the buffer regions (265) may efficiently replace aluminum as a terminal metal active region.

Abstract translation: 形成在复合半导体器件的金属化系统之上的凸起结构或柱结构可以包括应力缓冲层（260），其可以有效地分布由于这些的热失配而在芯片封装相互作用期间通常发生的所得到的机械应力 组件。 应力缓冲层（260）包括覆盖整个表面的重要部分的铜基缓冲区（265），其中也可以使用约3-10μm的厚度。 此外，缓冲区（265）可以有效地代替铝作为末端金属活性区。