公开(公告)号：WO2013028638A3

公开(公告)日：2013-02-28

申请号：PCT/US2012/051626

申请日：2012-08-20

Applicant: QUALCOMM INCORPORATED ,  ZUO, Chengjie ,  Yun, Changhan ,  KIM, Jonghae

Inventor： ZUO, Chengjie ,  Yun, Changhan ,  KIM, Jonghae

IPC: H03H9/02

Abstract: A resonator is described. The resonator includes multiple electrodes. The resonator also includes a composite piezoelectric material. The composite piezoelectric material includes at least one layer of a first piezoelectric material and at least one layer of a second piezoelectric material. At least one electrode is coupled to a bottom of the composite piezoelectric material. At least one electrode is coupled to a top of the composite piezoelectric material.

公开(公告)号：WO2013012638A1

公开(公告)日：2013-01-24

申请号：PCT/US2012/046293

申请日：2012-07-11

Applicant: QUALCOMM MEMS TECHNOLOGIES, INC. ,  ZUO, Chengjie ,  YUN, Changhan ,  LO, Chi Shun ,  KIM, Jonghae

Inventor： ZUO, Chengjie ,  YUN, Changhan ,  LO, Chi Shun ,  KIM, Jonghae

IPC: H03H9/02 ,  H03H9/17 ,  H03H3/02

CPC classification number: H03H9/02228 ,  H03H3/02 ,  H03H9/02055 ,  H03H9/173 ,  H03H2003/021 ,  Y10T29/42

Abstract: This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a resonator structure includes a first conductive layer of electrodes and a second conductive layer of electrodes. A piezoelectric layer including a piezoelectric material is disposed between the first conductive layer and the second conductive layer. One or more trenches can be formed in the piezoelectric layer on one or both sides in space regions between the electrodes. In some implementations, a process for forming the resonator structure includes removing an exposed portion of the piezoelectric layer to define a trench, for instance, by partial etching or performing an isotropic release etch using a XeF2 gas or SF6 plasma. In some other implementations, a portion of a sacrificial layer is removed to define a trench in the piezoelectric layer.

Abstract translation: 本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。 一方面，谐振器结构包括电极的第一导电层和电极的第二导电层。 包括压电材料的压电层设置在第一导电层和第二导电层之间。 一个或多个沟槽可以在电极之间的空间区域的一侧或两侧的压电层中形成。 在一些实施方案中，用于形成谐振器结构的工艺包括去除压电层的暴露部分以限定沟槽，例如通过部分蚀刻或使用XeF 2气体或SF 6等离子体进行各向同性释放蚀刻。 在一些其他实施方案中，去除牺牲层的一部分以在压电层中限定沟槽。

公开(公告)号：WO2012158889A1

公开(公告)日：2012-11-22

申请号：PCT/US2012/038308

申请日：2012-05-17

Applicant: QUALCOMM MEMS TECHNOLOGIES, INC. ,  YUN, Changhan ,  PARK, Sang-June ,  LO, Chi Shun ,  KIM, Jonghae ,  LAN, Je-Hsiung ,  JOO, Sanghoon

Inventor： YUN, Changhan ,  PARK, Sang-June ,  LO, Chi Shun ,  KIM, Jonghae ,  LAN, Je-Hsiung ,  JOO, Sanghoon

IPC: H03H9/17 ,  H03H9/02

CPC classification number: H03H9/173 ,  H03H9/02228

Abstract: This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, resonator apparatus includes a first conductive layer including a first electrode and a second electrode. The first electrode is coupled to receive a first input signal, and the second electrode is coupled to provide a first output signal. A piezoelectric layer includes a piezoelectric material. The piezoelectric layer has a first side and a second side opposite the first side. The first side is proximate the first conductive layer, and the second side is electrically isolated from ground. In some examples, the second side of the piezoelectric layer can be exposed and/or electrically de-coupled from one or more components.

Abstract translation: 本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。 在一个方面，谐振器装置包括包括第一电极和第二电极的第一导电层。 第一电极被耦合以接收第一输入信号，并且第二电极被耦合以提供第一输出信号。 压电层包括压电材料。 压电层具有与第一侧相对的第一侧和第二侧。 第一侧靠近第一导电层，第二侧与地电隔离。 在一些示例中，压电层的第二面可以暴露和/或从一个或多个部件电脱耦合。

公开(公告)号：WO2012040063A1

公开(公告)日：2012-03-29

申请号：PCT/US2011/052017

申请日：2011-09-16

Applicant: QUALCOMM MEMS TECHNOLOGIES, INC. ,  BLACK, Justin, Phelps ,  SHENOY, Ravindra, V. ,  GOUSEV, Evgeni, Petrovich ,  HADJICHRISTOS, Aristotele ,  MYERS, Thomas, Andrew ,  KIM, Jonghae ,  VELEZ, Mario, Francisco ,  LAN, Je-Hsiung, Jeffrey ,  LO, Chi, Shun

Inventor： BLACK, Justin, Phelps ,  SHENOY, Ravindra, V. ,  GOUSEV, Evgeni, Petrovich ,  HADJICHRISTOS, Aristotele ,  MYERS, Thomas, Andrew ,  KIM, Jonghae ,  VELEZ, Mario, Francisco ,  LAN, Je-Hsiung, Jeffrey ,  LO, Chi, Shun

IPC: H01L21/56 ,  G02B26/00

CPC classification number: G02B26/001 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/00

Abstract: This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.

Abstract translation: 本公开提供了用于组合沉积在第一衬底上的器件与形成在第二衬底（例如半导体衬底或玻璃衬底）上的集成电路的系统，方法和装置。 第一基板可以是玻璃基板。 第一衬底可以包括导电通孔。 功率组合器电路可以沉积在第一衬底的第一侧上。 功率组合器电路可以包括沉积在第一衬底的至少第一侧上的无源器件。 集成电路可以包括设置在功率合成器电路上并被配置为与功率组合器电路电连接的功率放大器电路，以形成功率放大系统。 导电通孔可以包括被配置为用于传导来自功率放大系统的热的热通孔和/或配置用于功率放大系统和第一衬底的第二侧上的导体之间的电连接的互连通孔。

公开(公告)号：WO2012030992A1

公开(公告)日：2012-03-08

申请号：PCT/US2011/050015

申请日：2011-08-31

Applicant: QUALCOMM Incorporated ,  WANG, Feng ,  GU, Shiqun ,  KIM, Jonghae ,  NOWAK, Matthew Michael

Inventor： WANG, Feng ,  GU, Shiqun ,  KIM, Jonghae ,  NOWAK, Matthew Michael

IPC: G06F13/16

CPC classification number: G06F13/1647 ,  G06F12/0607 ,  G06F13/1642 ,  G06F13/1657 ,  G06F2213/0064

Abstract: A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.

Abstract translation: 多个DRAM系统中的负载平衡包括跨两个或多个存储器通道交织存储器数据。 内存通道的访问由内存控制器控制。 总线主机通过互连系统耦合到存储器控制器，并且存储器请求从总线主机传送到存储器控制器。 如果在存储器通道中检测到拥塞，则产生拥塞信号并将其发送到总线主机。 因此，基于拥塞信号，存储器请求被相应地撤回或重新路由到较不拥塞的存储器通道。

公开(公告)号：WO2012030991A1

公开(公告)日：2012-03-08

申请号：PCT/US2011/050014

申请日：2011-08-31

Applicant: QUALCOMM INCORPORATED ,  WANG, Feng ,  GU, Shiqun ,  KIM, Jonghae ,  NOWAK, Matthew, Michael

Inventor： WANG, Feng ,  GU, Shiqun ,  KIM, Jonghae ,  NOWAK, Matthew, Michael

IPC: G06F13/16

CPC classification number: G06F13/1647 ,  G06F12/0607

Abstract: A non-uniform interleaving scheme in a multiple channel DRAM system comprises associating memory data with a memory address, associating address zones to predetermined ranges of memory addresses and associating predetermined interleaving granularities with the address zones. Memory data is interleaved across two or more memory channels such that a predetermined interleaving granularity is applied to each address zone.

Abstract translation: 多通道DRAM系统中的非均匀交织方案包括将存储器数据与存储器地址相关联，将地址区域与预定范围的存储器地址相关联，并将预定的交织粒度与地址区域相关联。 存储器数据在两个或更多个存储器通道之间交错，使得预定的交织粒度被应用于每个地址区。

公开(公告)号：WO2011088366A1

公开(公告)日：2011-07-21

申请号：PCT/US2011/021363

申请日：2011-01-14

Applicant: QUALCOMM Incorporated ,  CHANDRASEKARAN, Arvind ,  KIM, Jonghae

Inventor： CHANDRASEKARAN, Arvind ,  KIM, Jonghae

IPC: H05K1/02 ,  H05K3/34 ,  H05K1/16 ,  H01L23/64 ,  H01Q1/00

CPC classification number: H05K1/0239 ,  H01L23/552 ,  H01L23/66 ,  H01L25/0657 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K3/3436 ,  H05K2201/0723 ,  H05K2201/10098 ,  H05K2201/2036

Abstract: A passive device having a portion in the package substrate (1372, 582) and a portion in the system board (374, 584) such that the portions of the device are electromagnetically coupled. A transformer including inductors in the package substrate (372) and system board (374) electromagnetically coupled across a space between the substrate and board (370) that is surrounded by solder balls (320, 322) coupling the substrate and board. A capacitor including plates in the substrate (582) and board (584) electromagnetically coupled across a space between the substrate and board (580) that is surrounded by solder balls (520, 522) coupling the substrate and board. A core material (586, 376) can at least partially fill the space between the substrate and board. The solder balls surrounding the space can be coupled to ground. Metal shielding can be put in the substrate and/or board surrounding the device. The metal shielding can be coupled to the solder balls. The metal shielding can be coupled to ground.

Abstract translation: 一种无源器件，其具有在封装衬底（1372,582）中的一部分和系统板（374,584）中的部分，使得器件的部分电磁耦合。 一种变压器，包括在基板和板（370）之间的空间电磁耦合的封装基板（372）和系统板（374）中的电感器，所述空间由耦合所述基板和板的焊球（320,322）包围。 电容器包括在衬底（582）中的板和电路耦合在衬底和板（580）之间的空间的板（584），其被耦合衬底和板的焊球（520,522）包围。 核心材料（586,376）可以至少部分地填充衬底和板之间的空间。 围绕空间的焊球可以联接到地面。 可以将金属屏蔽放置在设备周围的基板和/或板中。 金属屏蔽可以耦合到焊球。 金属屏蔽可以耦合到地面。

公开(公告)号：WO2011044392A1

公开(公告)日：2011-04-14

申请号：PCT/US2010/051868

申请日：2010-10-07

Applicant: QUALCOMM Incorporated ,  KIM, Jonghae ,  GU, Shiqun ,  HENDERSON, Brian Matthew ,  TOMS, Thomas R. ,  CHUA-EOAN, Lew G. ,  BAZARJANI, Seyfollah S. ,  NOWAK, Matthew

Inventor： KIM, Jonghae ,  GU, Shiqun ,  HENDERSON, Brian Matthew ,  TOMS, Thomas R. ,  CHUA-EOAN, Lew G. ,  BAZARJANI, Seyfollah S. ,  NOWAK, Matthew

IPC: H01L21/02 ,  H01L23/522 ,  H01F17/00 ,  H01L27/06 ,  H01L23/48

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F19/04 ,  H01F2017/002 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0207 ,  H01L2224/16145 ,  H01L2924/3011

Abstract: A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments (704) of a first metal layer, a plurality of segments (706) of a second metal layer, a first inductor input (708) a second inductor input (710) and a plurality of through silicon vias (702) coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip

Abstract translation: 公开了三维片上电感器，变压器和射频放大器。 射频放大器包括一对变压器和晶体管。 变压器包括至少两个电感耦合电感器。 电感器包括第一金属层的多个段（704），第二金属层的多个段（706），第一电感器输入端（708），第二电感器输入端（710）和多个通孔硅通孔 （702），耦合所述第一金属层的所述多个段和所述第二金属层的所述多个段，以在所述第一电感器输入和所述第二电感器输入之间形成连续的，不相交的路径。 电感器可以具有对称或不对称的几何形状。 第一金属层可以是芯片的后端部分中的金属层。 第二金属层可以位于芯片的再分布设计层中

公开(公告)号：WO2011044390A1

公开(公告)日：2011-04-14

申请号：PCT/US2010/051866

申请日：2010-10-07

Applicant: QUALCOMM INCORPORATED ,  KIM, Jonghae ,  YANG, Jeong, Hwan ,  NOWAK, Matthew, M.

Inventor： KIM, Jonghae ,  YANG, Jeong, Hwan ,  NOWAK, Matthew, M.

IPC: H01L23/64 ,  H01L23/66 ,  H01L25/065 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/3011

Abstract: Methods and apparatuses for matching impedances in a flip-chip circuit assembly are presented. An apparatus for matching impedances in a flip-chip circuit assembly may include a first circuit associated with a first die and a through silicon via (TSV) coupling the first circuit to a second circuit. The apparatus may further include a first impedance matching inductor interposed between the TSV and the second circuit. A method for matching impedances in a flip-chip circuit assembly may include providing a die having a first circuit, and forming a TSV over the die. The method may further include providing a second circuit and forming a first impedance matching inductor interposed between the TSV and second circuit.

Abstract translation: 提出了用于匹配倒装芯片电路组件中的阻抗的方法和装置。 用于匹配倒装芯片电路组件中的阻抗的装置可以包括与第一管芯相连的第一电路和将第一电路耦合到第二电路的通硅通孔（TSV）。 该装置还可以包括插在TSV和第二电路之间的第一阻抗匹配电感器。 用于匹配倒装芯片电路组件中的阻抗的方法可以包括提供具有第一电路的管芯，并在管芯上形成TSV。 该方法还可以包括提供第二电路并形成插在TSV和第二电路之间的第一阻抗匹配电感器。

公开(公告)号：WO2011017628A1

公开(公告)日：2011-02-10

申请号：PCT/US2010/044736

申请日：2010-08-06

Applicant: QUALCOMM INCORPORATED ,  WANG, Feng ,  NOWAK, Matthew, Michael ,  KIM, Jonghae

Inventor： WANG, Feng ,  NOWAK, Matthew, Michael ,  KIM, Jonghae

IPC: G06F13/16 ,  G06F15/173

CPC classification number: G06F13/1663 ,  G06F13/1684 ,  Y02D10/14

Abstract: A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar interconnect. The method includes partitioning the crossbar interconnect into a plurality of partitions comprising at least a first partition corresponding to the first set of masters and a second partition corresponding to the second set of masters. The method also includes allocating a first set of buffer areas within the multi-channel memory. The first set of buffer areas correspond to the first set of masters. The method further includes allocating a second set of buffer areas within the multi-channel memory. The second set of buffers correspond to the second set of masters.

Abstract translation: 一种方法包括从多个主器件识别第一组主器件和第二组主器件。 多个主机通过交叉开关互连访问多通道存储器。 所述方法包括将所述交叉开关互连划分成多个分区，所述多个分区至少包括对应于所述第一组主机的第一分区和对应于所述第二组主机的第二分区。 该方法还包括在多通道存储器内分配第一组缓冲区。 第一组缓冲区对应于第一组主机。 该方法还包括在多通道存储器内分配第二组缓冲区。 第二组缓冲器对应于第二组主机。