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公开(公告)号：CA1320285C
公开(公告)日：1993-07-13
申请号：CA616246
申请日：1991-12-05
Applicant: PRIME COMPUTER INC
Inventor： LEFSKY BRIAN , NATUSCH MARY E
Abstract: HIGH AVAILABILITY CACHE MEMORY A high availability set associative cache memory for use as a buffer between a main memory and a central processing unit includes multiple sets of cache cells contained in two or more cache memory elements. Each of the cache cells includes a data field, a tag field and a status field. The status field includes a force bit which indicates a defective cache cell when it is set. Output from a cache cell is suppressed when its force bit is set. The defective cache cell is effectively mapped out so that data is not stored in it. As long as one cell in a set remains operational, the system can continue operation. The status field also includes an update bit which indicates the update status of the respective cache cell. Replacement selection logic examines the bit pattern in all the cache cells in a set and selects a cache cell to be replaced using a first-in first-out algorithm. The state of the update bit is changed each time the data in the respective cache cell is replaced unless the cache cell was modified on a previous store cycle.
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公开(公告)号：AU612636B2
公开(公告)日：1991-07-18
申请号：AU1418788
申请日：1988-04-05
Applicant: PRIME COMPUTER INC
Inventor： ALLISON ROBERT , LEFSKY BRIAN
IPC: G06F12/06
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公开(公告)号：DE3679214D1
公开(公告)日：1991-06-20
申请号：DE3679214
申请日：1986-02-13
Applicant: PRIME COMPUTER INC
Inventor： IRUKULLA SUREN , PATEL BIMAL V
Abstract: The invention provides a method and apparatus for radix- beta non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involves generating an initial radix- beta quotient digit from the transformed numerator. An iterative phase of the process generates successive partial remainders according to a recursive method. From the sign and a single radix- beta digit of each of these partial remainders, the process generates a radix- beta quotient digit. Further, a fourth phase, which may run concurrently with the transitional and iterative phases, involves accumulating succesively generated quotient digits to produce a final quotient value.
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公开(公告)号：AT63649T
公开(公告)日：1991-06-15
申请号：AT86300988
申请日：1986-02-13
Applicant: PRIME COMPUTER INC
Inventor： IRUKULLA SUREN , PATEL BIMAL V
Abstract: The invention provides a method and apparatus for radix- beta non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involves generating an initial radix- beta quotient digit from the transformed numerator. An iterative phase of the process generates successive partial remainders according to a recursive method. From the sign and a single radix- beta digit of each of these partial remainders, the process generates a radix- beta quotient digit. Further, a fourth phase, which may run concurrently with the transitional and iterative phases, involves accumulating succesively generated quotient digits to produce a final quotient value.
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公开(公告)号：AT62764T
公开(公告)日：1991-05-15
申请号：AT85300859
申请日：1985-02-08
Applicant: PRIME COMPUTER INC
Inventor： RODMAN PAUL K
IPC: G06F12/08 , G06F12/0817 , G06F12/0831 , G06F15/16 , G06F15/177
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Patent Agency Ranking
公开(公告)号：AT48487T
公开(公告)日：1989-12-15
申请号：AT84101376
申请日：1984-02-10
Applicant: PRIME COMPUTER INC
Inventor： LONG CHARLES COMEY , LOUNSBURY DAVID MORGAN , CURTIN RICHARD ROY
Abstract: Apparatus is disclosed for reading phase encoded digital data from a nine-track magnetic tape which apparatus includes timing circuitry for deriving a clock signal from the recorded data. A portion of the timing circuitry is associated with each track on the tape and automatically accomodates, without generating errors, phase changes in the derived clock signal in that track caused by speed variations in the magnetic tape transport and due to bit shifts caused by certain data patterns.Tape transport speed variations are sensed and the derived clock rate is corrected by a digital phase-locked loop which uses a counter that is clocked at a constant rate to determine the timing "window" during which the circuitry looks for signal transitions on the magnetic tape. A running average of the count remaining in the counter at the time when a transition actually occurs is used to adjust the counter starting value until equilibrium is established.The circuitry accomodates clock signal phase changes caused by bit shifting by calculating an expected arrival time for a data transition and varying the width of the timing window depending on whether the data transition is received either prior to or subsequent to the expected arrival time.
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公开(公告)号：CA1246231A
公开(公告)日：1988-12-06
申请号：CA447306
申请日：1984-02-13
Applicant: PRIME COMPUTER INC
Inventor： LONG CHARLES C , LOUNSBURY DAVID M , CURTIN RICHARD R
Abstract: Apparatus For Decoding Phase Encoded Data Apparatus is disclosed for reading phase encoded digital datafrom a nine-track magnetic tape which apparatus includes timing circuitry for deriving a clock signal from the recorded data. A portion of the timing circuitry is associated with each track on the tape and automatically accomodates, without generating errors, phase changes in the derived clock signal in that track caused by speed variations in the magnetic tape transport and due to bit shifts caused by certain data patterns. Tape transport speed variations are sensed and the derived clock rate is corrected by a digital phase-locked loop which uses a counter that is clocked at a constant rate to determine the timing ''window'' during which the circuitry looks for signal transitions on the magnetic tape. A running average of the count remaining in the counter at the time when a transition actually occurs is used to adjust the counter starting value until equilibrium is established. The circuitry accomodates clock signal phase changes caused by bit shifting by calculating an expected arrival time for a data transition and varying the width of the timing window depending on whether the data transition is received either prior to or subsequent to the expected arrival time.
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公开(公告)号：CA1243126A
公开(公告)日：1988-10-11
申请号：CA494234
申请日：1985-10-30
Applicant: PRIME COMPUTER INC
Inventor： YEN FANG-YING , GOLIN MARION A , SPILKE HOWARD , PETERS JEFF R
Abstract: A transactional data base processing apparatus which executes plural transactions causing a data base to be updated, incorporates an after-image recovery storage apparatus and method which enables continuous operation of the transaction system. The after-image recovery storage apparatus has a temporary storage file and a permanent storage file with circuitry for writing from the temporary storage file to the permanent storage file. That circuitry also writes after-image updating data records to the temporary storage file. The apparatus further includes elements for initiating transfer of the after-image data records from the temporary storage file to the permanent storage prior to a time when the temporary file is filled with the data records. The transfer is accomplished by operating the apparatus on a time shared basis so that other ongoing operations including transactional operations occur as the after-image data is being transferred to a permanent storage device.
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公开(公告)号：CA1233905A
公开(公告)日：1988-03-08
申请号：CA473962
申请日：1985-02-08
Applicant: PRIME COMPUTER INC
Inventor： CURTIN RICHARD R , CLEMENTE PAUL M
Abstract: Digital circuitry performs arithmetic operations upon first and second binary coded decimal digit strings input thereto. The digital circuitry provides for receiving and storing first and second BCD digit, the digits having an arbitrary data type format. The first and second data types are selected from the group of packed and unpacked data. The circuitry then performs the arithmetic operation upon the stored BCD digits to obtain a result data word which is made available in a data type format corresponding to a selected one of the input BCD digits. In a particular embodiment, a plurality of the circuits can be operated in a digit slice structure. The digit slice structure operates upon strings of packed, unpacked, and mixed data type arithmetic operands and provides, at its output lines, output data in a format corresponding to a selected input data type. In particular a unique interconnection of the plural output lines of the circuitry enables the output data type to be packed or unpacked as desired. The circuitry also provides for automatic selection of digits applied to the circuitry thereby relieving the operating environment from significant time consuming and costly supervision.
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公开(公告)号：CA1309181C
公开(公告)日：1992-10-20
申请号：CA563909
申请日：1988-04-12
Applicant: PRIME COMPUTER INC
Inventor： LEFSKY BRIAN , NATUSCH MARY E
Abstract: HIGH AVAILABILITY CACHE MEMORY A high availability set associative cache memory for use as a buffer between a main memory and a central processing unit includes multiple sets of cache cells contained in two or more cache memory elements. Each of the cache cells includes a data field, a tag field and a status field. The status field includes a force bit which indicates a defective cache cell when it is set. Output from a cache cell is suppressed when its force bit is set. The defective cache cell is effectively mapped out so that data is not stored in it. As long as one cell in a set remains operational, the system can continue operation. The status field also includes an update bit which indicates the update status of the respective cache cell. Replacement selection logic examines the bit pattern in all the cache cells in a set and selects a cache cell to be replaced using a first-in first-out algorithm. The state of the update bit is changed each time the data in the respective cache cell is replaced unless the cache cell was modified on a previous store cycle.
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