公开(公告)号：US06509229B1

公开(公告)日：2003-01-21

申请号：US09850484

申请日：2001-05-07

Applicant: Fei Wang ,  Ramkumar Subramanian ,  Yu Sun

Inventor： Fei Wang ,  Ramkumar Subramanian ,  Yu Sun

IPC: H01L21336

CPC classification number: H01L21/76897 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2924/3011

Abstract: A method for shrinking a semiconductor device is disclosed. An etch stop layer is eliminated and is replaced with a consumable second sidewall spacers so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. In a preferred embodiment, the present invention provides a method for forming self-aligned contacts by forming multi-layer structures on a region on a semiconductor substrate, forming first sidewall spacers around the multi-layer structures, forming second sidewall spacers around the first sidewall spacers, forming a dielectric layer directly over the substrate and in contact with second sidewall spacers, forming an opening in the dielectric layer to expose a portion of the region on the semiconductor substrate adjacent the second sidewall spacers, and filling the opening with a conductive material to form a contact.

Abstract translation: 公开了一种用于收缩半导体器件的方法。 消除了蚀刻停止层，并且被可消耗的第二侧壁间隔物代替，使得该器件的堆叠栅极结构可以更靠近地放置在一起，从而允许器件收缩。 在优选实施例中，本发明提供了一种通过在半导体衬底上的区域上形成多层结构来形成自对准接触的方法，在多层结构周围形成第一侧墙，围绕第一侧壁形成第二侧壁 间隔物，直接在衬底上形成电介质层并与第二侧壁间隔物接触，在电介质层中形成开口以暴露与第二侧壁间隔物相邻的半导体衬底上的区域的一部分，并用导电材料填充该开口 形成联系。

公开(公告)号：US06507474B1

公开(公告)日：2003-01-14

申请号：US09597126

申请日：2000-06-19

Applicant: Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bryan K. Choo ,  Bharath Rangarajan

Inventor： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bryan K. Choo ,  Bharath Rangarajan

IPC: H01T2300

CPC classification number: G03F7/70616 ,  G03F7/70941

Abstract: One aspect of the present invention elates to a method of reducing electrostatic charges on a patterned photoresist to improve evaluation of the developed photoresist, involving the steps of evaluating the patterned photoresist to determine if electrostatic charges exist thereon; positioning an ionizer near the patterned photoresist, the ionizer generating ions thereby reducing the electrostatic charges on the patterned photoresist; and evaluating the patterned photoresist with an electron beam. Another aspect of the present invention relates to a system for reducing electrostatic charges on a patterned photoresist, containing a charge sensor for determining if electrostatic charges exist on the patterned photoresist and measuring the electrostatic charges; an ionizer positioned near the patterned photoresist having electrostatic charges thereon for reducing the electrostatic charges on the patterned photoresist; a controller for setting at least one of time of ion generation and amount of ion generation by the ionizer, the controller coupled to the charge sensor and the ionizer; and a scanning electron microscope or an atomic force microscope for evaluating the patterned photoresist having reduced electrostatic charges thereon with an electron beam.

Abstract translation: 本发明的一个方面是提供减少图案化光致抗蚀剂上的静电电荷以改进对显影光致抗蚀剂的评估的方法，包括评估图案化光致抗蚀剂以确定静电电荷是否存在于其中的步骤; 在图案化的光致抗蚀剂附近定位电离器，离子发生器产生离子，从而减少图案化光致抗蚀剂上的静电电荷; 并用电子束评估图案化的光致抗蚀剂。 本发明的另一方面涉及一种用于减少图案化光致抗蚀剂上的静电电荷的系统，其包含用于确定图案化光致抗蚀剂上是否存在静电电荷并测量静电电荷的电荷传感器; 位于图案化的光致抗蚀剂附近的电离器，其上具有静电电荷，用于减少图案化光致抗蚀剂上的静电电荷; 用于设置离子发生时间和离子发生量中的至少一个的控制器，耦合到电荷传感器和离子发生器的控制器; 以及扫描电子显微镜或原子力显微镜，用于用电子束评估其上具有降低的静电电荷的图案化光致抗蚀剂。

公开(公告)号：US06492075B1

公开(公告)日：2002-12-10

申请号：US09881993

申请日：2001-06-15

Applicant: Michael K. Templeton ,  Ramkumar Subramanian ,  Bharath Rangarajan

Inventor： Michael K. Templeton ,  Ramkumar Subramanian ,  Bharath Rangarajan

IPC: G03H900

CPC classification number: G03F7/40 ,  G03F7/405

Abstract: In one embodiment, the present invention relates to a method of treating a patterned resist involving the steps of providing the patterned resist having structural features of a first size, the patterned resist containing a polymer having a labile group; contacting a coating containing at least one cleaving compound with the patterned resist to form a thin deprotected resist layer at an interface between the patterned resist and the coating; and removing the coating and the thin deprotected resist layer leaving the patterned resist having structural features of a second size, wherein the second size is smaller than the first size.

Abstract translation: 在一个实施方案中，本发明涉及一种处理图案化抗蚀剂的方法，包括以下步骤：提供具有第一尺寸结构特征的图案化抗蚀剂，所述图案化抗蚀剂含有具有不稳定基团的聚合物; 使含有至少一种裂解化合物的涂层与图案化的抗蚀剂接触以在图案化的抗蚀剂和涂层之间的界面处形成薄的去保护的抗蚀剂层; 以及去除涂层和薄的去保护的抗蚀剂层，留下具有第二尺寸的结构特征的图案化抗蚀剂，其中第二尺寸小于第一尺寸。

公开(公告)号：US06482699B1

公开(公告)日：2002-11-19

申请号：US09685972

申请日：2000-10-10

Applicant: YongZhong Hu ,  Fei Wang ,  Wenge Yang ,  Yu Sun ,  Ramkumar Subramanian

Inventor： YongZhong Hu ,  Fei Wang ,  Wenge Yang ,  Yu Sun ,  Ramkumar Subramanian

IPC: H01L21336

CPC classification number: H01L21/76897 ,  H01L21/76895 ,  H01L2924/3011

Abstract: A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A first and second photoresist contact masks are deposited, processed, and used to respectively etch core and peripheral contact openings. The first and photoresist contact masks are respectively removed after each etching step. A conductive material is deposited over the dielectric layer and in the core and peripheral contact openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings with core contacts to the source/drain regions and peripheral contacts to the local interconnect gate contacts of the multi-layer structures and the source/drain regions.

Abstract translation: 提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。 在多层结构周围形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。 第一和第二光致抗蚀剂接触掩模被沉积，处理并用于分别蚀刻芯部和外围接触开口。 在每个蚀刻步骤之后分别去除第一和光致抗蚀剂接触掩模。 导电材料沉积在电介质层上以及芯和外围接触开口中，并进行化学机械平面化以去除电介质层上的导电材料，因此导电材料在核心和外围接触开口中被隔离，其核心接触到 源极/漏极区域和周边接触到多层结构和源极/漏极区域的局部互连栅极触点。

公开(公告)号：US06482558B1

公开(公告)日：2002-11-19

申请号：US09782382

申请日：2001-02-12

Applicant: Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan

Inventor： Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan

IPC: G03F900

CPC classification number: G03F7/093 ,  G03F1/40 ,  G03F1/50 ,  Y10S430/143

Abstract: One aspect of the present invention relates to a system for dissipating electrostatic charge on a mask plate structure containing the mask plate structure containing a substrate, a chromium layer over the substrate, and a conductive polymer over the chromium layer; a conductive structure coupled to the mask plate structure which allows accumulated electrostatic charge to flow from the mask plate structure; a conductive path between the conductive structure and a ground, wherein the conductive path inacludes a switch controlled by a controller; and a detector coupled to the controller for signaling the controller when the accumulation of electrostatic charge is detected. Another aspect of the present invention relates to a method for dissipating charge accumulation during patterning of mask plates using a conductive polymer layer involving the steps of providing a mask substrate having a chromium layer; depositing a conductive polymer layer over the chromium layer; connecting a conductive structure to the mask substrate; irradiating portions of the mask substrate with an electron beam; detecting whether electrostatic charge exists on the mask substrate; and if electrostatic charge is detected, closing a circuit whereby the conductive structure is grounded to permit a flow of electrostatic charge from the mask substrate to the ground.

Abstract translation: 本发明的一个方面涉及一种用于在掩模板结构上耗散静电电荷的系统，该系统包含含有衬底的掩模板结构，在衬底上的铬层和在铬层上的导电聚合物; 耦合到掩模板结构的导电结构，其允许积聚的静电电荷从掩模板结构流动; 导电结构和地之间的导电路径，其中导电路径不允许由控制器控制的开关; 以及耦合到控制器的检测器，用于在检测到静电电荷的累积时用于发信号通知控制器。 本发明的另一方面涉及一种使用导电聚合物层在掩模板图案化期间耗散电荷累积的方法，包括以下步骤：提供具有铬层的掩模基板; 在所述铬层上沉积导电聚合物层; 将导电结构连接到所述掩模基板; 用电子束照射掩模基板的部分; 检测在掩模基板上是否存在静电电荷; 并且如果检测到静电电荷，则关闭电路，由此导电结构接地以允许静电电荷从掩模基板流到地面。

公开(公告)号：US06475904B2

公开(公告)日：2002-11-05

申请号：US09204166

申请日：1998-12-03

Applicant: Uzodinma Okoroanyanwu ,  Ramkumar Subramanian

Inventor： Uzodinma Okoroanyanwu ,  Ramkumar Subramanian

IPC: H01L214763

CPC classification number: H01L21/02343 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/02321 ,  H01L21/02359 ,  H01L21/31144 ,  H01L21/3121 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76832

Abstract: A damascene structure and method of making the same in a low k dielectric material employs an imageable layer in which the damascene pattern is provided. The imageable layer is an alicyclic polymer into which silicon is incorporated by liquid silylation, for example. The silicon-rich regions are converted upon exposure to the plasma etch that etches the low k dielectric material into a hard mask containing silicon dioxide, for example. The low k dielectric material is protected from further etching by the mask thus created.

Abstract translation: 一种镶嵌结构及其在低k电介质材料中的制造方法采用其中提供镶嵌图案的可成像层。 可成像层是例如通过液体硅烷化引入硅的脂环族聚合物。 富含氟的区域在暴露于例如将低k电介质材料蚀刻成含有二氧化硅的硬掩模的等离子体蚀刻时被转换。 通过由此产生的掩模来保护低k电介质材料免于进一步蚀刻。

公开(公告)号：US06459155B1

公开(公告)日：2002-10-01

申请号：US09729528

申请日：2000-12-05

Applicant: Ramkumar Subramanian ,  Dawn M. Hopper ,  Minh Van Ngo

Inventor： Ramkumar Subramanian ,  Dawn M. Hopper ,  Minh Van Ngo

IPC: H01L214763

CPC classification number: H01L21/76829 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/76807

Abstract: The dimensional accuracy of trench formation and, hence, metal line width, in damascene technology is improved by employing a low Si—SiON etch stop layer/ARC with reduced etch selectivity with respect to the overlying dielectric material but having a reduced extinction coefficient (k). Embodiments include via first-trench last dual damascene techniques employing a low Si—SiON middle etch stop layer/ARC having an extinction coefficient of about −0.3 to about −0.6, e.g., about −0.35, with reduced silicon and increased oxygen vis-à-vis a SiON etch stop layer having an extinction coefficient of about −1.1. Embodiments also include removing about 60% to about 90% of the low Si—SiON etch stop layer/ARC during trench formation, thereby reducing capacitance.

Abstract translation: 通过使用低Si-SiON蚀刻停止层/ ARC，相对于上覆电介质材料具有降低的蚀刻选择性但具有降低的消光系数（k（k）），改善了镶嵌技术中沟槽形成的尺寸精度以及因此金属线宽度 ）。 实施例包括通过第一沟槽最后的双镶嵌技术，其使用具有约-0.3至约-0.6，例如约-0.35的消光系数的低Si-SiON中间蚀刻停止层/ ARC，其中还原的硅和增加的氧相对于 - 具有约-1.1的消光系数的SiON蚀刻停止层。 实施例还包括在沟槽形成期间去除约60％至约90％的低Si-SiON蚀刻停止层/ ARC，从而降低电容。

公开(公告)号：US06458691B1

公开(公告)日：2002-10-01

申请号：US09824662

申请日：2001-04-04

Applicant: Ramkumar Subramanian ,  Christopher F. Lyons ,  Marina V. Plat ,  Bhanwar Singh

Inventor： Ramkumar Subramanian ,  Christopher F. Lyons ,  Marina V. Plat ,  Bhanwar Singh

IPC: H01L214763

CPC classification number: H01L21/31144 ,  H01L21/76807

Abstract: There is provided a method of making a dual inlaid via in a first layer. The first layer may be a polymer intermetal dielectric, such as HSQ, of a semiconductor device. The method includes forming a first opening, such as a via, in the first layer and forming an inorganic base radiation sensitive layer in the first opening. The radiation sensitive layer may be a polysilane imaging layer. The inorganic base radiation sensitive layer is selectively exposed to radiation and then patterned. A second opening, such a trench, is formed in communication with the first opening using the patterned inorganic base radiation sensitive layer as a mask. A conductive layer may be formed in the dual inlaid via to complete a dual damascene process.

Abstract translation: 提供了在第一层中制作双重嵌入通孔的方法。 第一层可以是半导体器件的聚合物金属间电介质，例如HSQ。 该方法包括在第一层中形成诸如通孔的第一开口，并在第一开口中形成无机碱辐射敏感层。 辐射敏感层可以是聚硅烷成像层。 无机碱辐射敏感层选择性地暴露于辐射，然后图案化。 使用图案化的无机基底辐射敏感层作为掩模，形成与第一开口连通的第二开口，这样的沟槽。 可以在双镶嵌通孔中形成导电层以完成双镶嵌工艺。

公开(公告)号：US06455409B1

公开(公告)日：2002-09-24

申请号：US09793992

申请日：2001-02-28

Applicant: Ramkumar Subramanian ,  Dawn M. Hopper

Inventor： Ramkumar Subramanian ,  Dawn M. Hopper

IPC: H01L214763

CPC classification number: H01L21/76831 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76843 ,  H01L21/76873 ,  H01L2221/1036

Abstract: Damascene techniques are implemented using a silicon carbide bard mask to prevent contact between an organic photoresist mask and dielectric material, particularly a low-K dielectric material. Embodiments include etching using a silicon carbide hard mask to form a via opening through a low-K ILD, depositing an overlying ILD, e.g., another low-K ILD, forming a capping layer on the second ILD and etching to form a trench in communication with the underlying via opening to complete the dual damascene opening.

Abstract translation: 使用碳化硅ard掩模实现镶嵌技术以防止有机光致抗蚀剂掩模和电介质材料，特别是低K电介质材料之间的接触。 实施例包括使用碳化硅硬掩模进行蚀刻，以通过低K ILD形成通孔，沉积上层ILD，例如在第二ILD上形成覆盖层的另外的低K ILD，并进行蚀刻以形成沟通沟槽 底部的通孔开口完成双镶嵌开口。

公开(公告)号：US06444373B1

公开(公告)日：2002-09-03

申请号：US09596954

申请日：2000-06-16

Applicant: Ramkumar Subramanian ,  Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan

Inventor： Ramkumar Subramanian ,  Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan

IPC: G03F900

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70441

Abstract: The present invention relates to a system and method of modifying mask layout data to improve the fidelity of mask manufacture. The system and method include determining the difference between the mask layout design and the mask features as written, and generating sizing corrections. The sizing corrections can be used to modify the mask layout data, and/or stored in a database.

Abstract translation: 本发明涉及一种修改掩模布局数据以提高掩模制造的保真度的系统和方法。 该系统和方法包括确定掩模布局设计和掩模特征之间的写入差异，并产生尺寸校正。 尺寸校正可用于修改掩模布局数据和/或存储在数据库中。