Temperature-compensated scintillation detector, temperature compensation circuit and method
    31.
    发明专利
    Temperature-compensated scintillation detector, temperature compensation circuit and method 审中-公开
    温度补偿型扫描检测器,温度补偿电路及方法

    公开(公告)号:JP2008102159A

    公开(公告)日:2008-05-01

    申请号:JP2008008445

    申请日:2008-01-17

    Inventor: ROZSA CSABA M

    CPC classification number: G01T1/202

    Abstract: PROBLEM TO BE SOLVED: To provide a circuit and a method, for temperature compensation of a temperature-dependent component of a scintillation detector for improving temperature compensation performance of the detector.
    SOLUTION: This scintillation detector wherein sensitivity to temperature is reduced has two circuits for the temperature compensation. The two circuits can be a circuit comprising both of a resistance element and a switching element, and a circuit comprising a thermistor connected thereto in parallel. The switching element can be a diverse element including a zener diode, a Schottky barrier diode, or an MIM (metal-insulator-metal). The circuits for the temperature compensation are included in a circuit of a photodetector such as a photomultiplier.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种用于温度补偿用于改善检测器的温度补偿性能的闪烁检测器的温度依赖性部件的电路和方法。 解决方案:该温度敏感度降低的闪烁检测器具有用于温度补偿的两个电路。 两个电路可以是包括电阻元件和开关元件的电路,以及包括并联连接到其上的热敏电阻的电路。 开关元件可以是包括齐纳二极管,肖特基势垒二极管或MIM(金属 - 绝缘体 - 金属))的多种元件。 用于温度补偿的电路包括在诸如光电倍增管的光电检测器的电路中。 版权所有(C)2008,JPO&INPIT

    Wafer carrier having improved processing characteristic
    39.
    发明专利
    Wafer carrier having improved processing characteristic 审中-公开
    具有改进加工特性的滚动架

    公开(公告)号:JP2010103554A

    公开(公告)日:2010-05-06

    申请号:JP2009295992

    申请日:2009-12-25

    CPC classification number: H01L21/67326

    Abstract: PROBLEM TO BE SOLVED: To provide a wafer carrier which is suitable for improved processing operations that provide improved device yield and low defectivity. SOLUTION: The wafer carrier 1 for supporting a plurality of wafers vertically includes at least first, second, and third support members 10, 12 and 14, and a plurality of slots 16 for receiving the plurality of wafers. The first, the second, and the third support members 10, 12 and 14 are provided so as to support and contact the wafers, and each slot is made up of first, second and third slot segments 18, 20 and 22, respectively, each of which respectively being extended along the first, the second and the third support members 10, 12, and 14. A cradle 2 is comprised of silicon carbide and has an oxide layer covering the silicon carbide. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种适用于提高设备产量和低缺陷性的改进处理操作的晶片载体。 解决方案:用于支撑多个晶片的晶片载体1垂直地包括至少第一,第二和第三支撑构件10,12和14以及用于容纳多个晶片的多个狭槽16。 第一,第二和第三支撑构件10,12和14设置成支撑和接触晶片,并且每个槽分别由第一,第二和第三槽段18,20和22组成,每个 其分别沿着第一,第二和第三支撑构件10,12和14延伸。支架2由碳化硅构成,并且具有覆盖碳化硅的氧化物层。 版权所有(C)2010,JPO&INPIT

Patent Agency Ranking