公开(公告)号：WO2007115146A3

公开(公告)日：2008-04-24

申请号：PCT/US2007065604

申请日：2007-03-30

Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

IPC: H02H9/00

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

Abstract translation: 芯片包括CMOS结构，该CMOS结构具有布置在半导体衬底（50）的第一区域（24）中的与衬底的下方体区（18）导电连通的体装置（20），第一区域（24）和 该体区域（20）具有第一晶体取向。 SOI器件（10）设置在绝缘体上半导体（“SOI”）层（14）中，所述绝缘体上半导体（SOI）层通过掩埋介电层（16）与衬底的体区分开，SOI层具有与 第一个晶体取向。 在一个示例中，大容量器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，大容量器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与大容量器件的栅极导体（21）导电连通的栅极导体（11）时，除了存在二极管与SOI器件的反向偏置传导通信之外，SOI器件可能会发生充电损坏 地区。 当栅极导体上的电压或SOI器件的源极或漏极区上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导至体区。

公开(公告)号：WO2005117085A3

公开(公告)日：2006-10-12

申请号：PCT/US2005018050

申请日：2005-05-23

Applicant: IBM ,  STAMPER ANTHONY K

Inventor： STAMPER ANTHONY K

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/31116 ,  H01L21/76807 ,  H01L28/87

Abstract: A method of forming a semiconductor device, and the device so formed. Depositing alternating layers of a first dielectric material (12a-f) and a second dielectric material (14a-f), wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature (22, 24) within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material to remove at least a portion (26) of the first dielectric material in each layer having the first dielectric material and leaving the second dielectric material as essentially unetched.

Abstract translation: 形成半导体器件的方法以及如此形成的器件。 沉积第一介电材料（12a-f）和第二介电材料（14a-f）的交替层，其中所述第一和第二介电材料可以以不同的速率被选择性地蚀刻。 在电介质材料的交替层内形成第一特征（22,24）。 选择性地蚀刻介电材料的交替层以去除具有第一电介质材料的每层中的第一介电材料的至少一部分（26），并使第二介电材料基本上未被蚀刻。

公开(公告)号：WO2006060212A1

公开(公告)日：2006-06-08

申请号：PCT/US2005/042088

申请日：2005-11-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ADKISSON, James, W. ,  GAMBINO, Jeffrey, P. ,  JAFFE, Mark, D. ,  LEIDY, Robert, K. ,  STAMPER, Anthony, K.

Inventor： ADKISSON, James, W. ,  GAMBINO, Jeffrey, P. ,  JAFFE, Mark, D. ,  LEIDY, Robert, K. ,  STAMPER, Anthony, K.

IPC: H01L31/062 ,  H01L21/00

CPC classification number: H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

Abstract: A CMOS image sensor array (100) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (M1, M2) allowing for incorporation of a thinner interlevel dielectric stack (13 Oa-c) with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure (135a, 135b) formed at locations between each array pixel and, a barrier material layer (132a, 132b) is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening (51) is then refilled with dielectric material (150). Prior to depositing the refill dielectric, a layer of either reflective or absorptive material (140) is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode (18) or by eliminating light reflections.

Abstract translation: CMOS图像传感器阵列（100）及其制造方法，其中传感器包括铜（Cu）金属化水平（M1，M2），允许结合更薄的层间电介质堆叠（13a-c），具有改善的厚度均匀性，从而导致 显示增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括形成在每个阵列像素之间的位置处的Cu金属线结构（135a，135b），并且在每个Cu金属线结构上方形成阻挡材料层（132a，132b） 像素光路。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 蚀刻的开口（51）然后用电介质材料（150）重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层（140），以通过将光反射到下面的光电二极管（18）或通过消除光反射来提高像素的灵敏度。