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    Finite field based short error propagation modulation code
    31.
    发明专利
    Finite field based short error propagation modulation code 审中-公开
    基于有限域的短错误传播调制码

    公开(公告)号：JP2006172708A

    公开(公告)日：2006-06-29

    申请号：JP2005361301

    申请日：2005-12-15

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc

    Inventor： BLISS WILLIAM G ,  KARABED RAZMIK

    IPC: G11B20/14 ,  G11B20/10 ,  G11B20/18 ,  H03M13/01

    CPC classification number: G11B20/10194 ,  G11B20/10009 ,  G11B20/1426 ,  G11B20/1833 ,  G11B2220/2516

    Abstract: PROBLEM TO BE SOLVED: To provide signal modulation technology in which flexibility is improved.
    SOLUTION: The invention provides a data modulation method applicable to make data streams tend to have desired properties, useful for clock recovery, making signals more distinguishable, or enforcing run-length conditions. A stream of input data and a corresponding stream of output data grouped into elements of a finite field. Input elements of the input data are modified by a transform generating output elements of the output data, such that a current output element is linear combination of current input element and at least one previous output element. A multiplier applied to at least one previous output element is non-zero and non-unity element of the finite field. A set of initial conditions inherent to the transform is selected such that the output elements resulting from the transform tend to have the desired property.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供灵活性提高的信号调制技术。 解决方案：本发明提供了一种适用于使数据流倾向于具有期望特性的数据调制方法，对于时钟恢复有用，使得信号更加可区分或执行运行长度条件。 输入数据流和分组为有限域的元素的输出数据的相应流。 通过产生输出数据的输出元件的变换来修改输入数据的输入元件，使得当前输出元件是当前输入元件和至少一个先前输出元件的线性组合。 应用于至少一个先前输出元素的乘数是有限域的非零和非单位元素。 选择变换固有的一组初始条件，使得由变换产生的输出元素倾向于具有期望的属性。 版权所有（C）2006，JPO＆NCIPI

    Write driver with power optimization and interconnect impedance matching
    32.
    发明专利
    Write driver with power optimization and interconnect impedance matching 审中-公开
    具有功率优化和互连阻塞匹配的写驱动器

    公开(公告)号：JP2005302286A

    公开(公告)日：2005-10-27

    申请号：JP2005117072

    申请日：2005-04-14

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc

    Inventor： VENCA ALESANDRO ,  ALINI ROBERTO ,  POSAT BARIS

    IPC: G11B5/09 ,  G05F3/26 ,  G11B5/02 ,  H04L25/02

    CPC classification number: G11B5/02

    Abstract: PROBLEM TO BE SOLVED: To improve a write head in a hard disk drive system by providing impedance matching and a power amplification effect.
    SOLUTION: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line is provided. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：通过提供阻抗匹配和功率放大效果来改善硬盘驱动器系统中的写入头。 解决方案：提供一种用于通过互连或柔性传输线连接到写入头的写入头来驱动写入电流的写入驱动器。 写驱动器包括将写驱动器的输出阻抗与互连的奇特特性阻抗匹配的电路，并且包括产生到写头的电流输出的电流源。 写入驱动器提供电流放大效应，因为输出电流是通过写入线圈驱动的写入电流的一半。 阻抗匹配电路包括具有等于互连的奇特性阻抗的电阻的输出电阻器。 写入驱动器包括电压源，其操作以在互连的传输延迟的两倍的初始周期期间在输出电阻器上保持零电压降。 版权所有（C）2006，JPO＆NCIPI

    Magnitude content addressable memory
    34.
    发明专利
    Magnitude content addressable memory 有权
    MAGNITUDE内容可寻址记忆

    公开(公告)号：JP2005129218A

    公开(公告)日：2005-05-19

    申请号：JP2004307123

    申请日：2004-10-21

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

    Inventor： LYSINGER MARK

    IPC: G11C15/04 ,  G06F7/02 ,  G11C15/00

    CPC classification number: G06F7/026 ,  G11C15/00

    Abstract: PROBLEM TO BE SOLVED: To provide a magnitude content addressable memory (MCAM). SOLUTION: Each cell of MCAM includes a data memory cell for storing data value and a magnitude comparator coupled to a first memory cell. The magnitude comparator receives a data value and a comparison value as inputs, and produces two magnitude signals as outputs. The first magnitude signal indicates whether the comparison value is greater than the data value and the second magnitude signal indicates whether the comparison value is less than the data value. The magnitude comparator also receives magnitude signals from the preceding MCAM cell. The previous magnitude signals are outputted as the first and second magnitude signals when the data value and the comparison value are equal. The MCAM enables data words of arbitrary length to be compared with comparison words. The MCAM cell may contain a second memory for storing a mask value. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供幅度内容可寻址存储器（MCAM）。 解决方案：MCAM的每个单元包括用于存储数据值的数据存储单元和耦合到第一存储单元的幅度比较器。 幅度比较器接收数据值和比较值作为输入，并产生两个幅度信号作为输出。 第一幅度信号指示比较值是否大于数据值，第二幅度信号指示比较值是否小于数据值。 幅度比较器还从前面的MCAM单元接收幅度信号。 当数据值和比较值相等时，先前的幅度信号作为第一和第二幅度信号被输出。 MCAM使任意长度的数据字与比较字进行比较。 MCAM单元可以包含用于存储掩码值的第二存储器。 版权所有（C）2005，JPO＆NCIPI

    Smart card including jtag test controller and related method
    36.
    发明专利
    Smart card including jtag test controller and related method 审中-公开
    智能卡包括JTAG测试控制器及相关方法

    公开(公告)号：JP2005004765A

    公开(公告)日：2005-01-06

    申请号：JP2004171135

    申请日：2004-06-09

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

    Inventor： LEAMING TAYLOR J

    IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06K7/00 ,  G06K19/07

    CPC classification number: G01R31/318555 ,  G01R31/3025 ,  G01R31/31719 ,  G06F11/267 ,  G06F11/27 ,  G06K7/0013 ,  G06K7/0095 ,  G06K7/10465 ,  G06K19/07 ,  G06K19/07733

    Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit for a smart card having improved test performance and to provide a related method. SOLUTION: According to the present invention, the integrated circuit for a smart card includes a transceiver which communicates with a host device and a joint test action group (JTAG) test controller for carrying out at least one test operation. Further, the integrated circuit can include a processor which allows the JTAG test controller to start the at least one test operation based on the reception of at least one test request from the host device via the transceiver. More specifically, the processor can convert the at least one test request into JTAG data for the JTAG test controller. Namely, the integrated circuit enables communications between the host device and the JTAG controller via a system bus without the need for a dedicated JTAG test access port (TAP) typically required for accessing the JTAG controller. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供具有改进的测试性能的智能卡的集成电路并提供相关方法。 解决方案：根据本发明，用于智能卡的集成电路包括与主机设备和用于执行至少一个测试操作的联合测试动作组（JTAG）测试控制器通信的收发器。 此外，集成电路可以包括处理器，其允许JTAG测试控制器基于经由收发器从主机设备接收至少一个测试请求来开始至少一个测试操作。 更具体地，处理器可以将至少一个测试请求转换为用于JTAG测试控制器的JTAG数据。 也就是说，集成电路通过系统总线实现主机设备和JTAG控制器之间的通信，而不需要通常需要访问JTAG控制器的专用JTAG测试访问端口（TAP）。 版权所有（C）2005，JPO＆NCIPI

    System for testing smart card, and related method
    37.
    发明专利
    System for testing smart card, and related method 审中-公开
    用于测试智能卡的系统及相关方法

    公开(公告)号：JP2005004762A

    公开(公告)日：2005-01-06

    申请号：JP2004170423

    申请日：2004-06-08

    Applicant: Stmicroelectronics Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッド STMicroelectronics,Inc

    Inventor： LEAMING TAYLOR J

    IPC: G06K17/00 ,  G06K7/00 ,  G06K19/07

    CPC classification number: G06F11/263 ,  G06K7/0013 ,  G06K7/0095 ,  G06K7/10465 ,  G06K19/07

    Abstract: PROBLEM TO BE SOLVED: To provide an improved method of developing and testing smart cards. SOLUTION: A system relating tests design of a universal serial bus (USB) smart card device and contains a bus analyzer for running a test case to generate a USB bus traffic. A processor is connected to the bus analyzer for receiving data of the USB traffic and converting them into data format chosen usable over a different smart card developing environment. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供开发和测试智能卡的改进方法。 解决方案：一种与通用串行总线（USB）智能卡设备的测试设计相关的系统，并且包含用于运行测试用例的总线分析器以产生USB总线流量。 处理器连接到总线分析器，用于接收USB流量的数据，并将其转换为可选择通过不同的智能卡开发环境使用的数据格式。 版权所有（C）2005，JPO＆NCIPI

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