公开(公告)号：US20020176233A1

公开(公告)日：2002-11-28

申请号：US10085121

申请日：2002-02-27

Applicant: STMicroelectronics Limited

Inventor： Paul Evans

IPC: H05K007/00

CPC classification number: H01R12/523 ,  H05K1/144

Abstract: A stackable module for a processor system including a support plate with a set of topside circuit components mounted to its topside, and topside and underside connectors. The module is stackable with other such modules and are provided with conductive tracks that are arranged to convey transport stream data and transport stream control signals between modules in a stack. A stack of such modules in a processor system is also provided.

Abstract translation: 一种用于处理器系统的可堆叠模块，其包括具有安装到其顶侧的一组顶侧电路部件的支撑板以及顶侧和下侧连接器。 该模块可与其他这样的模块堆叠并且设置有导电轨道，其被布置成在堆叠中的模块之间传送传输流数据和传输流控制信号。 还提供了处理器系统中的这种模块的堆叠。

公开(公告)号：US20020146130A1

公开(公告)日：2002-10-10

申请号：US10099589

申请日：2002-03-13

Applicant: STMicroelectronics Limited

Inventor： Andrew R. Dellow

IPC: H04L009/00

CPC classification number: H04N21/462 ,  H04N5/76 ,  H04N5/913 ,  H04N21/4334 ,  H04N21/434 ,  H04N21/4408 ,  H04N2005/91364

Abstract: A device for locating a DES key value that corresponds to a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header. A table stored in memory contains for each DES key: (i) a packet header having 32 bits with a PID of either 12, 9 or 8 bits contained at a defined location and with zero values elsewhere, and (ii) a mask value also having 32 bits with ones contained at the said defined location of the PID and zeros elsewhere. The table is divided into regions for respective packet format types. An incoming packet header at an input is combined with a first one of the mask values from the table to provide a combined value that consists of the value held in the input packet header at the defined location and zeros elsewhere. This combined value is compared with the corresponding packet header stored in the table. When they are not equal, the combining and comparison is repeated for the next row of the table. When they are equal, the corresponding DES key value is read from the table and provided as an output. The system can cope with variable PID formats within the packet header without alteration to the hardware but merely with re-programming of the table contents.

Abstract translation: 用于定位对应于包含在可变可能位置的分组标识（PID）的DES密钥值的设备，该可变位置仅包括32位分组报头的一部分。 存储在存储器中的表包含每个DES密钥：（i）具有32位的分组报头，其中包含在定义的位置处的12,9或8位的PID，并且在其他地方具有零值，以及（ii）掩码值 具有32位，其中包含在PID的所述定义的位置处，并且其他地方具有零。 该表被分成用于相应分组格式类型的区域。 在输入处的输入分组报头与表中的第一个掩码值组合，以提供组合值，该组合值由保存在定义位置的输入分组报头中的值和其他地方的零组成。 将该组合值与存储在表中的相应分组报头进行比较。 当它们不相等时，对于表的下一行重复组合和比较。 当它们相等时，从表中读取相应的DES密钥值作为输出。 该系统可以处理数据包头中的可变PID格式，而不会改变硬件，但只能对表内容进行重新编程。

公开(公告)号：US20040122881A1

公开(公告)日：2004-06-24

申请号：US10632530

申请日：2003-08-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.l.

Inventor： Philip Mattos ,  Marco Losi

IPC: G06F017/15

CPC classification number: G01S19/37 ,  G01S19/24 ,  G01S19/29 ,  G01S19/30 ,  H04B1/708 ,  H04B1/709 ,  H04B2201/70715

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a memory arrangement comprising two circulating shift registers circulates samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators. The same correlators are thereby used to increase acquisition speed.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，包括两个循环移位寄存器的存储装置循环接收信号的采样，以便与本地生成的GPS码版本相关。 在跟踪模式中，采样信号被直接提供给相关器。 因此，使用相同的相关器来提高采集速度。

公开(公告)号：US20040004977A1

公开(公告)日：2004-01-08

申请号：US10421317

申请日：2003-04-22

Applicant: STMicroelectronics Limited

Inventor： William Robbins ,  David Wilkins

IPC: H04J003/04

CPC classification number: H04N21/434

Abstract: There is disclosed a circuit and method for demultiplexing in a receiver a digital data stream including at least two types of data, so as to retain only those parts of the digital data stream required by the receiver. In one particular application, such a receiver is used in a television system having a digital set-top-box receiver. A first control circuit extracts a packet identifier from an input data packet in the digital data stream, and generates a signal in dependence on whether the input data packet is of the first or second type. Sets of information associated with the first types of data packets and required by the receiver are stored in a memory under the control of a second control circuit. A third control circuit, responsive to receipt of the first type of input data packet, determines whether at least part of the input data packet matches the stored sets of information, and sets a match signal responsive thereto.

Abstract translation: 公开了一种用于在接收机中解复用包括至少两种数据的数字数据流的电路和方法，以便仅保留接收机所需的数字数据流的那些部分。 在一个特定应用中，这种接收机用在具有数字机顶盒接收机的电视系统中。 第一控制电路从数字数据流中的输入数据包中提取分组标识符，并根据输入数据分组是第一类还是第二类产生信号。 在第二控制电路的控制下，与第一类型的数据分组相关联并且由接收机所要求的信息集存储在存储器中。 响应于接收到第一类型的输入数据分组的第三控制电路确定输入数据分组的至少一部分是否与存储的信息组匹配，并且响应于此设置匹配信号。

公开(公告)号：US20030056164A1

公开(公告)日：2003-03-20

申请号：US09954637

申请日：2001-09-14

Applicant: STMicroelectronics Limited

Inventor： Christophe Lauga

IPC: G01R031/28

CPC classification number: G01R31/318536 ,  G01R31/318547 ,  G01R31/318572

Abstract: A semiconductor integrated circuit, including a test scan arrangement has a plurality of scan chains arranged in pairs. These scan chains have input terminals for receiving test patterns, and outputs provided to compression logic such as a distributed XOR tree multiple input shift register to provide an output which is a compressed signal derived from the output test patterns. In an alternative configuration, the first scan chain of each pair is connected to the second scan chain of each pair, and the input terminal of the second scan chain becomes the output terminal. Thereby creating a longer scan chain of the first and second scan chains together with one input terminal and one output terminal. The two loads allow for efficient scanning in the first mode, or debugging to determine the position of a fault in the second mode.

Abstract translation: 包括测试扫描装置的半导体集成电路具有成对布置的多个扫描链。 这些扫描链具有用于接收测试图案的输入端子，以及提供给诸如分布式异或树多输入移位寄存器之类的压缩逻辑的输出，以提供作为从输出测试图案导出的压缩信号的输出。 在替代配置中，每对的第一扫描链连接到每对的第二扫描链，并且第二扫描链的输入端变为输出端。 从而创建第一和第二扫描链的更长的扫描链以及一个输入端和一个输出端。 两个负载允许在第一模式下进行有效的扫描，或者调试以确定第二模式中故障的位置。

公开(公告)号：US20020196710A1

公开(公告)日：2002-12-26

申请号：US10157731

申请日：2002-05-29

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow ,  Paul Elliott

IPC: G06F001/04 ,  G04F005/00

CPC classification number: G06F1/08

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract translation: 用于根据切换请求信号选择第一时钟信号A或第二时钟信号B的时钟源选择器包括三个重新定时电路，每个由两个时钟触发器组成。 开关请求信号相对于时钟A首先被重新定时以给出信号P，相对于时钟B被重新定时以给出信号Q，并且最后相对于时钟A被重新定时以给出信号R.选择器电路操作使得当 信号Q被置位，当第二时钟信号B被输出时，当由或非门组合的信号P和信号R都不被断言时，输出第一时钟信号A，并且在其它时间输出零电平。 时钟源选择器可用于集成电路中以形成无毛刺多路复用器。

公开(公告)号：US20020191725A1

公开(公告)日：2002-12-19

申请号：US10106899

申请日：2002-03-25

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: H03D003/24

CPC classification number: H03D13/004

Abstract: A digital phase comparator circuit that determines and adjusts the relative phase of two digital clock signals derived from the same digital clock. The circuit having two inputs, one connected to receive each of the clock signals to be compared and including a latch circuit to receive one clock signal at the clock input, and the other clock signal at a data input. The latch circuit is arranged so that the output is equal to the signal at the data input when measured at the clock edge. The output is therefore a logic null1null when the second clock leads the first clock, and a logic null0null when the second clock lags the first clock.

Abstract translation: 数字相位比较器电路，用于确定并调整从相同数字时钟导出的两个数字时钟信号的相对相位。 该电路具有两个输入端，一个连接到接收要比较的每个时钟信号，并且包括用于在时钟输入端接收一个时钟信号的锁存电路，以及数据输入端的另一个时钟信号。 锁存电路被布置为使得当在时钟边沿测量时，输出等于数据输入端的信号。 因此，当第二个时钟引导第一个时钟时，输出为逻辑“1”，当第二个时钟延迟第一个时钟时，输出为逻辑“0”。

公开(公告)号：US20020005733A1

公开(公告)日：2002-01-17

申请号：US09949703

申请日：2001-09-10

Applicant: STMicroelectronics Limited

Inventor： William B. Barnes

IPC: H03K017/16

CPC classification number: H01L29/0634 ,  H03K3/356113 ,  H03K17/102

Abstract: A switching circuit is discussed that has an improved switching time in comparison with switching circuits of a known type. The circuit comprises three switches connected in series, the first switch being connected to an upper power supply and the third switch being connected to a lower power supply. The output of the circuit is connected to a circuit node located at the connection between the second and third switch. The input to the switching circuit is also connected to the third switch and additionally connected to a control circuit which provides a further output to control the first switch. The second switch is responsive to the voltage at the circuit node such that the second switch only conducts when the voltage at the output node falls below the upper supply voltage. This has the effect that the first switch is effectively isolated from the third switch during switching and allows a time delay during which the first switch is switched off under control of the control circuit and the second switch switches on. The provision of the voltage dependent second switch eliminates any nullcurrent battlesnull occurring between the first and third switch during switching.

Abstract translation: 讨论了与已知类型的开关电路相比具有改进的开关时间的开关电路。 电路包括串联连接的三个开关，第一开关连接到上电源，第三开关连接到较低电源。 电路的输出连接到位于第二和第三开关之间的连接处的电路节点。 开关电路的输入也连接到第三开关，并且还连接到控制电路，该控制电路提供另外的输出以控制第一开关。 第二开关响应于电路节点处的电压，使得第二开关仅在输出节点处的电压下降到低于上电源电压时才导通。 这具有在开关期间第一开关与第三开关有效隔离的作用，并且允许第一开关在控制电路的控制下被切断并且第二开关导通的时间延迟。 提供依赖于电压的第二开关消除了在切换期间在第一和第三开关之间发生的任何“当前的战斗”。

公开(公告)号：US20040156507A1

公开(公告)日：2004-08-12

申请号：US10705782

申请日：2003-11-10

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow ,  Rodrigo Cordero

IPC: H04L009/00

CPC classification number: H04N21/42623 ,  H04N21/26613 ,  H04N21/4623

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals, the circuit including an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with the television signals include control words and common keys. The common keys are received in encrypted form, encrypted according to a secret key unique to each semiconductor integrated circuit. The input interface is connected to a decryption circuit whereby the only manner of providing the common keys to the circuit are in encrypted form encrypted according to the secret key. Due to the monolithic nature of the circuit, no secrets are exposed and the system is secure.

Abstract translation: 一种用于处理条件接收电视信号的半导体集成电路，该电路包括用于接收加密的电视信号的输入接口和用于输出解密的电视信号的输出接口。 用电视信号广播的控制信号包括控制字和公共密钥。 公共密钥以加密形式接收，根据每个半导体集成电路独有的秘密密钥进行加密。 输入接口连接到解密电路，由此向电路提供公共密钥的唯一方式是根据密钥加密的加密形式。 由于电路的整体性质，没有暴露的秘密和系统是安全的。

公开(公告)号：US20040148583A1

公开(公告)日：2004-07-29

申请号：US10352799

申请日：2003-01-27

Applicant: STMicroelectronics Limited

Inventor： Andrew Hulbert ,  Enrico Gregoratto

IPC: G06F017/50

CPC classification number: G06F17/5068 ,  G06F17/505

Abstract: A method of arranging an integrated circuit to correct for hold time errors comprises fixing the position of existing cells in a design, determining hold time errors required to be corrected and placing buffer cells in spaces in the existing design. By placing buffer cells in spaces in the existing design, rather than moving cells in the existing design, the hold time can be corrected without changing the critical path.

Abstract translation: 布置集成电路以校正保持时间误差的方法包括：将设计中的现有单元的位置固定，确定需要校正的保持时间误差，并将缓冲单元放置在现有设计中的空格中。 通过将现有设计中的缓冲区放置在空格中，而不是在现有设计中移动单元格，可以在不改变关键路径的情况下更正保持时间。