公开(公告)号：KR1019920004921B1

公开(公告)日：1992-06-22

申请号：KR1019890013188

申请日：1989-09-12

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 주범순 ,  이창문 ,  이정희 ,  김옥희

IPC: H03K19/00

Abstract: The circuit includes a TMR (triple modular redundancy) circuit (1) for receiving synchronizing clock codes to output selection information for normally operating synchronizing clocks. A clock receiving circuit (2) receives triplexed synchronizing clocks from a synchronizing clock generating section. A monitor circuit (3) monitors the state of the triplexed synchronizing clocks to output an information on it. A PROM (4) outputs code values for the synchronizing clocks, and a multiplexer (5) receives the triplexed synchronizing signals, and outputs the signals selected by the output values of the PROM (4). With the circuit, no separate clock selecting data is required.

Abstract translation: 该电路包括用于接收同步时钟代码以输出用于正常操作的同步时钟的选择信息的TMR（三模块冗余）电路（1）。 时钟接收电路（2）从同步时钟产生部分接收三重同步时钟。 监视器电路（3）监视三相同步时钟的状态以输出关于它的信息。 PROM（4）输出同步时钟的代码值，多路复用器（5）接收三路同步信号，并输出由PROM（4）的输出值选择的信号。 使用该电路，不需要单独的时钟选择数据。

公开(公告)号：KR1019920003362B1

公开(公告)日：1992-04-30

申请号：KR1019890012900

申请日：1989-09-06

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 박권철 ,  이정희 ,  주범순 ,  김옥희

IPC: H04L7/00

Abstract: A checking finds whether the current PLL (phase locked loop) is a master PLL or a slave PLL, and a proper action is taken depending on the checked result. If the phase difference of the PLL is not maintained at zero for a certain minimum period, the function for it is instantly stopped. During the occurrence of phase difference, the function is not carried out, but accumulates the input signals, and then, terminates the operation. If the phase difference data of the slave PLL is kept stable at zero for a certain period of time, an adjustment is carried out. When the output data level is shifted from "H" to "L", the phase is slowed down, but, when the data level is shifted from "L" to "H", an opposite action is carried out.

Abstract translation: 检查发现当前PLL（锁相环）是主PLL还是从PLL，并根据检查结果采取适当的动作。 如果PLL的相位差在一定的最小时间内没有保持为零，则其功能立即停止。 在发生相位差时，不执行该功能，而是累积输入信号，然后终止动作。 如果从PLL的相位差数据在一定时间段内保持为零，则进行调整。 当输出数据电平从“H”移位到“L”时，相位减慢，但是当数据电平从“L”移位到“H”时，执行相反的动作。