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公开(公告)号：KR1020090063592A
公开(公告)日：2009-06-18
申请号：KR1020070131020
申请日：2007-12-14
IPC: H04B7/26
CPC classification number: H04L5/0053 , H04L1/004 , H04L5/0058 , H04W52/04 , H04W72/042
Abstract: An apparatus for efficiently decoding one or more control channel in a mobile communications terminal is provided to decode control channel data according to the kind of control channel received to the mobile communication terminal. A control information channel decoder(110) decodes control information channel data corresponding to a bit number. A downlink control channel decoder(120) decodes downlink control channel data by using a data block corresponding to the number of bits. A feedback channel decoder(130) decodes feedback channel data corresponding to bit repetition information. A transmission power control channel decoder(140) decodes transmission power control channel data corresponding to an encoding sequence.
Abstract translation: 提供一种用于在移动通信终端中有效解码一个或多个控制信道的装置，以根据接收到移动通信终端的控制信道的种类对控制信道数据进行解码。 控制信息信道解码器（110）解码对应于比特数的控制信息信道数据。 下行链路控制信道解码器（120）通过使用对应于比特数的数据块来解码下行链路控制信道数据。 反馈信道解码器（130）解码对应于比特重复信息的反馈信道数据。 发送功率控制信道解码器（140）解码对应于编码序列的发送功率控制信道数据。
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公开(公告)号：KR1020090063004A
公开(公告)日：2009-06-17
申请号：KR1020070130509
申请日：2007-12-13
IPC: H04W28/22
Abstract: A derate matching method and an apparatus therefor are provided to simultaneously derate-match a plurality of large sized data, thereby shortening a derate matching time. A derate matching apparatus successively stores received data(S300). The derate matching apparatus calculates the number of bits to be derate-matched initially among the received data and performs derate matching(S310). The derate matching apparatus repeats a derate matching process until variables, I and K, become the same(S320). The derate matching apparatus combines accumulated bits to be derate-matched while the variable I becomes from 1 to K in order to generate output data(S330).
Abstract translation: 提供一种降额匹配方法及其装置，用于同时降低匹配多个大尺寸数据，从而缩短降额匹配时间。 降级匹配装置依次存储接收的数据（S300）。 降额匹配装置计算在接收数据中最初降级匹配的比特数，并执行降级匹配（S310）。 降额匹配装置重复降额匹配过程，直到变量I和K变得相同（S320）。 为了产生输出数据，降额匹配装置将累加的比特组合为降序匹配，同时变量I从1变为K，以产生输出数据（S330）。
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公开(公告)号：KR1020090059430A
公开(公告)日：2009-06-11
申请号：KR1020070126290
申请日：2007-12-06
CPC classification number: H04L1/0013 , H03M13/2778 , H03M13/2792
Abstract: An apparatus and a method for processing a signal are provided to consecutively encode a plurality of code blocks by collecting a rate matching result bit of an information bit and a parity bit into a bit stream. An encoder(150) encodes an input signal, and outputs an information bit, a first parity bit, and a second parity bit. A rate matching device(160) collects a rate matching result bit of the information bit, the first parity bit, and the second parity bit into a bit stream while rate-matching the information bit, the first parity bit, and the second parity bit. A block interleaver(170) block-interleaves the bit stream. A collecting period and a block interleaving period are overlapped.
Abstract translation: 提供了一种用于处理信号的装置和方法，用于通过将信息比特和奇偶校验比特的速率匹配结果比特收集到比特流中来对多个码块进行连续编码。 编码器（150）对输入信号进行编码，并输出信息比特，第一奇偶校验位和第二奇偶校验位。 速率匹配装置（160）将信息比特，第一奇偶校验位和第二奇偶校验比特的速率匹配结果比特收集到比特流中，同时对信息比特，第一奇偶校验位和第二奇偶校验位进行速率匹配 。 块交织器（170）块比特流进行交织。 收集周期和块交织周期重叠。
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公开(公告)号：KR100809438B1
公开(公告)日：2008-03-05
申请号：KR1020070019905
申请日：2007-02-27
Applicant: 한국전자통신연구원
IPC: H04L12/28 , H04L29/06 , H04L12/741 , H04B10/25
CPC classification number: H04L45/745 , H04L49/354 , H04Q11/0067
Abstract: An apparatus and a method for processing a VLAN frame for terminal control within a GPON system are provided to indirectly connect information about a terminal of a GPON(Gigabit Passive Optical Network) slave party in a switch by connecting terminated port ID information within a GPON master device to an upper switch through VLAN tag frame processing, thereby performing inter-complement between the GPON master device and the switch. An apparatus for processing a VLAN frame comprises the follows. An uplink input unit(221) receives uplink data, including a VLAN(Virtual Local Area Network) tag frame corresponding to port ID(Identification) information in a GPON(Gigabit Passive Optical Network) system, from a GPON master device(210). An uplink processor(222) extracts a VLAN ID from the VLAN tag frame, stores an MAC(Media Access Control) address of a termination terminal device as an origination address of the uplink data in an MAC table(223) together with the extracted VLAN ID, and transmits the uplink data to an upper switch(230). The MAC table stores the MAC address information of the terminal device and the VLAN ID information by learning or initial CPU(Central Processing Unit) setup. A downlink input unit(224) receives downlink data going to a lower GPON system from the switch. A downlink lookup unit(225) searches a destination address of the received downlink data from the MAC table, and confirms VLAN ID corresponding to the destination address. A downlink processor(226) includes the confirmed VLAN ID in the downlink data as a tag frame, and transmits the downlink frame to the GPON master device.
Abstract translation: 提供了一种用于处理GPON系统中终端控制的VLAN帧的装置和方法，用于通过连接GPON主机中的端接端口ID信息来间接连接交换机中GPON（千兆位无源光网络）从属终端的信息 设备通过VLAN标签帧处理到上层交换机，从而在GPON主设备和交换机之间进行互补。 一种用于处理VLAN帧的装置包括以下。 上行链路输入单元（221）从GPON主设备（210）接收包括与GPON（千兆位无源光网络）系统中的端口ID（识别）信息相对应的VLAN（虚拟局域网））标签帧的上行链路数据。 上行链路处理器（222）从VLAN标签帧中提取VLAN ID，将终端终端设备的MAC（媒体访问控制）地址与提取的VLAN一起存储在MAC表（223）中作为上行链路数据的始发地址 ID，并将上行链路数据发送到上层交换机（230）。 MAC表通过学习或初始CPU（中央处理单元）设置来存储终端设备的MAC地址信息和VLAN ID信息。 下行链路输入单元（224）从交换机接收去往较低GPON系统的下行链路数据。 下行链路查找单元（225）从MAC表搜索接收到的下行链路数据的目的地址，并确认与目的地址对应的VLAN ID。 下行链路处理器（226）将下行链路数据中确认的VLAN ID作为标签帧，并将下行链路帧发送到GPON主设备。
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公开(公告)号：KR100462478B1
公开(公告)日：2004-12-17
申请号：KR1020020078148
申请日：2002-12-10
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A method for transceiving a variable-length packet is provided to enable a transmission circuit to know length of a packet to be transmitted before transmitting packet data, and to enable a CPU to know the length of the packet before reading the packet data, thereby easily programming software for realizing a variable-length packet transceiving function. CONSTITUTION: If an outer CPU tries to transmit a variable length packet, the CPU transmits the packet to a transmission data FIFO, so that the transmission data FIFO can store the packet(S210). The transmission data FIFO stores length information of the received packet in a transmission size FIFO(S220). As soon as size information is written in the transmission size FIFO, a transmission packet counter storage increases a transmission packet counter by 1, and informs a transmission circuit that the one packet is written(S230). The transmission circuit firstly reads the length information of the packet from the transmission size FIFO, and reads the substantial packet from the transmission data FIFO (S240). The transmission packet counter storage monitors a read signal, and decreases the transmission packet counter by 1 after reading the one packet(S250).
Abstract translation: 目的：提供一种用于收发可变长度分组的方法，以使发送电路在发送分组数据之前知道要发送的分组的长度，并使CPU在读取分组数据之前知道该分组的长度， 从而容易地编程用于实现可变长度分组收发功能的软件。 构成：如果外部CPU尝试发送可变长度分组，则CPU将分组发送到发送数据FIFO，使得发送数据FIFO可以存储分组（S210）。 传输数据FIFO将接收到的分组的长度信息存储在传输大小FIFO中（S220）。 一旦大小信息被写入传输大小FIFO中，传输包计数器存储器将传输包计数器增加1，并通知传输电路该一个包被写入（S230）。 传输电路首先从传输大小FIFO中读取分组的长度信息，并从传输数据FIFO中读取实质分组（S240）。 发送分组计数器存储器监视读取信号，并且在读取一个分组之后将发送分组计数器减1（S250）。
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Patent Agency Ranking
公开(公告)号：KR1020020054235A
公开(公告)日：2002-07-06
申请号：KR1020000083269
申请日：2000-12-27
Applicant: 한국전자통신연구원
IPC: G06F15/167
CPC classification number: H04L49/201 , H04L49/103 , H04L49/3018 , H04L49/3027
Abstract: PURPOSE: A multi-casting system and method is provided to move contents of a pointer of an input queue to plural output queues for multi-casting the pointer, an address where data is stored, at a maximum speed, and to maintain a consistency of a memory value in the case of continuously reading a counter in a memory, modifying and writing the counter. CONSTITUTION: The system comprises an input queue reader(10), a queue number converter(20) and an output queue writer(30). The input queue reader(10) reads each byte of data at an output port bit map, outputs class data with an enable signal and the output port data, and maintains a current output data stream without a stop by reading the input queue previously in the case that the input queue is in a waiting state. The queue number converter(20) encodes bit map type output port data input by the input queue reader, collects the class data, makes a queue number of the output queue, and outputs the queue number with an enable number. The output queue writer(30) receives non using addresses of the output queue by using the data input via the queue number converter(20), writes the non using addresses at a tail of the output queue, and replaces the tail address, used at the next time, with a new non using address for writing a corresponding address at a corresponding output queue.
Abstract translation: 目的：提供一种多投影系统和方法，用于将输入队列的指针的内容移动到多个输出队列，以便以最大速度多次投射指针，存储数据的地址，并保持一致性 在存储器中连续读取计数器的情况下的存储器值，修改和写入计数器。 构成：系统包括输入队列读取器（10），队列号转换器（20）和输出队列写入器（30）。 输入队列读取器（10）在输出端口位图读取数据的每个字节，通过使能信号和输出端口数据输出类数据，并且通过先前在读取器中读取输入队列来维持当前输出数据流而不停止 情况是输入队列处于等待状态。 队列号转换器（20）编码由输入队列读取器输入的位图类型输出端口数据，收集类数据，输出队列号，并输出队列号与启用号码。 输出队列写入器（30）通过使用通过队列号转换器（20）输入的数据来接收输出队列的非使用地址，将非使用地址写入输出队列的尾部，并替换尾部地址 下一次，使用新的非使用地址在相应的输出队列中写入相应的地址。
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公开(公告)号：KR1020020053976A
公开(公告)日：2002-07-06
申请号：KR1020000082250
申请日：2000-12-26
Applicant: 한국전자통신연구원
IPC: H04L12/28
CPC classification number: H04L12/5601 , H04L2012/5605 , H04L2012/561 , H04L2012/5615
Abstract: PURPOSE: An ATM passive optical network optical network unit controller is provided to use an arbitrary MAC method by externally outputting an enable signal for a mini-slot payload, receiving a byte input signal, carrying an arbitrary data on the mini-slot and transmitting it. CONSTITUTION: A cell receiving unit(50) receives a data to externally transmits an ATM cell through a receiving utopia interface unit, and transmits a message carried on a PLOAM(Physical Layer Operation And Maintenance) cell. A cell transmitting unit(52) receives the ATM cell through a transmission utopia interface unit to carry it on a permitted slot, and carrying a message in a standby state in a message processing unit on a payload of the PLOAM cell and transmits it upwardly and downwardly in case of transmitting the PLOAM cell. A message processing unit(54) processes received various messages to set an internal signal, instructs operations of a plurality of function blocks, and transmits a message requested from the plurality of function blocks through the cell transmitting unit(52).
Abstract translation: 目的：提供ATM无源光网络光网络单元控制器，通过外部输出微时隙有效载荷的使能信号，接收字节输入信号，在微时隙上携带任意数据并发送它，使用任意的MAC方法 。 构成：小区接收单元（50）通过接收乌托邦接口单元接收外部外部发送ATM信元的数据，并发送在PLOAM（物理层操作与维护）单元上携带的消息。 小区发送单元（52）通过发送乌托邦接口单元接收ATM信元，将其携带在允许的时隙上，并且在消息处理单元中在PLOAM小区的有效载荷上携带处于待机状态的消息，并将其向上发送，并且 在发送PLOAM信元的情况下向下。 消息处理单元（54）处理接收到的各种消息以设置内部信号，指示多个功能块的操作，并通过小区发送单元（52）发送从多个功能块请求的消息。
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公开(公告)号：KR1020010001985A
公开(公告)日：2001-01-05
申请号：KR1019990021545
申请日：1999-06-10
Applicant: 한국전자통신연구원
IPC: H04L12/28
CPC classification number: H04L12/5601 , H04L2012/5635 , H04L2012/5652
Abstract: PURPOSE: The apparatus for removing lost packet data in order to prevent traffic congestion in an asynchronous transfer mode(ATM) system is provided to enable a stable ATM operation, and to guarantee the service with good quality for various types of service traffic, by preventing the traffic congestion in the system using minimum hardware logic. CONSTITUTION: A received cell processor(B2) generates a connection memory address(S2) related to a received cell(S1), a packet start signal and a packet end signal(S3). A connection table managing part(B3) manages an unnecessary cell designating signal(S5) and a negotiation parameter(S4). A negotiation violation checking part(B4) detects the cell that excesses a negotiated traffic rate, and sets the signal(S5) according to the result of the detection. An unnecessary cell processor(B5) combines the unnecessary cell designating signal(S5) received from the part(B3) with a negotiation violation signal(S6) applied from the part(B4), and thereby removes the unnecessary cell.
Abstract translation: 目的：为了防止异步传输模式（ATM）系统中的流量拥塞，用于消除丢失的分组数据的装置被提供以实现稳定的ATM操作，并通过防止各种类型的服务流量来保证具有良好质量的服务 系统中的交通拥堵使用最小的硬件逻辑。 构成：接收到的小区处理器（B2）生成与接收到的小区（S1）相关的连接存储器地址（S2），分组开始信号和分组结束信号（S3）。 连接表管理部（B3）管理不必要的小区指定信号（S5）和协商参数（S4）。 协商违反检查部（B4）检测超过协商的业务速率的小区，并根据检测结果来设定信号（S5）。 不必要的单元处理器（B5）将从部分（B3）接收的不必要的单元指定信号（S5）与从部分（B4）应用的协商冲突信号（S6）组合，从而去除不必要的单元。
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公开(公告)号：KR1020010001984A
公开(公告)日：2001-01-05
申请号：KR1019990021544
申请日：1999-06-10
Applicant: 한국전자통신연구원
IPC: H04L12/28
CPC classification number: H04L12/5601 , H04L2012/562 , H04L2012/5625 , H04L2012/5653
Abstract: PURPOSE: The apparatus for processing the function of an asynchronous transfer mode(ATM) layer is provided to suggest an ATM device competitive in cost and function, by implementing the functions for buffering quality of service(QOS) of a traffic, processing operation and management(OAM), and controlling a usage parameter and controlling the traffic, in a single ASIC chip. CONSTITUTION: A connection part(B2) generates a memory address for reception connection. A reception connection managing table(B3) stores a processed parameter value. A reception routing controller(B6) is connected to the table(B3), an OAM processor(B5) and a usage parameter controller(B4). An output controller(B7) is connected between the controller(B6) and a connection part(B10). A test cell generator(B8) creates an ATM cell. A controller(B9) multiplexes cells according to a priority order. A connection part(B12) generates a memory address for transmission connection. A transmission routing controller(B14) stores input cells in a priority order queue. A transmission cell multiplex controller(B18) multiplexes a loop-back cell according to its priority order.
Abstract translation: 目的：提供用于处理异步传输模式（ATM）层功能的装置，通过实现缓冲业务质量（QOS），处理操作和管理功能，提出ATM设备的成本和功能竞争力 （OAM），并且在单个ASIC芯片中控制使用参数并控制流量。 构成：连接部分（B2）产生用于接收连接的存储器地址。 接收连接管理表（B3）存储经处理的参数值。 接收路由控制器（B6）连接到表（B3），OAM处理器（B5）和使用参数控制器（B4）。 输出控制器（B7）连接在控制器（B6）和连接部件（B10）之间。 测试单元发生器（B8）创建一个ATM信元。 控制器（B9）根据优先级顺序复用单元。 连接部（B12）生成用于传输连接的存储器地址。 传输路由控制器（B14）将输入单元存储在优先级顺序队列中。 传输单元复用控制器（B18）根据其优先级顺序复用环回小区。
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公开(公告)号：KR100256679B1
公开(公告)日：2000-05-15
申请号：KR1019970073035
申请日：1997-12-24
IPC: H04L12/28
Abstract: PURPOSE: An ATM cell segmentation apparatus is provided to obtain a high performance with a minimum intervention of a host CPU by managing every control information for a plurality of connections, performing an ATM segmentation and creating a cell by directly reading a memory access master. CONSTITUTION: A buffer connection managing unit(200) connects buffer descriptor information transmitted from a host to a VC(Virtual Channel) table and increases reading addresses in a transmit queue by hardware. A scheduling and segmentation unit(210) requests a DMA(Direct Memory Access) from the buffer connection managing unit(200) by using AAL(ATM Adaptation Layer) associated information recorded in the VC table and the buffer descriptor information connected to the VC table, so as to fetch a data from the host memory, and generates a cell of each connection in an order previously set in a rate table while updating the VC table when the DMA is finished. A free descriptor managing unit(220) manages a buffer descriptor which is not connected to any VC table among buffer descriptors with a linked list. A UBR(Unspecified Bit Rate) pointer searching unit(230) searches a VC table entry address of a UBR connection to be next serviced for an UBR VC table, so that when the scheduling and segmentation unit(210) requests a UBR pointer, it can obtain the UBR pointer promptly, and if there is no CBR(Constant Bit Rate) and a VBR(Variable Bit Rate) data, a cell of a UBR connection can be transmitted without delay. A state reporting managing unit(240) records state information at a circulative position of a state queue of a local memory and interrupts a host CPU when the scheduling and segmentation unit(210) transmits a state reporting request signal along with state reporting information.
Abstract translation: 目的：提供ATM信元分割装置，通过管理多个连接的每个控制信息，通过直接读取存储器存取主机来执行ATM分段和创建单元，以主机CPU的最小干预来获得高性能。 构成：缓冲器连接管理单元（200）将从主机发送的缓冲区描述符信息连接到VC（虚拟通道）表，并通过硬件增加发送队列中的读取地址。 调度和分割单元（210）通过使用记录在VC表中的AAL（ATM适配层）关联信息和连接到VC表的缓冲器描述符信息来从缓冲器连接管理单元（200）请求DMA（直接存储器访问） ，以便从主机存储器获取数据，并且当DMA完成时更新VC表时，以先前在速率表中设置的顺序生成每个连接的单元。 空闲描述符管理单元（220）管理缓冲区描述符，该缓冲区描述符在具有链表的缓冲区描述符中未连接到任何VC表。 UBR（未指定比特率）指针搜索单元（230）在UBR VC表中搜索下一个维修的UBR连接的VC表入口地址，使得当调度和分段单元（210）请求UBR指针时， 可以及时获取UBR指针，如果没有CBR（Constant Bit Rate，固定比特率）和VBR（Variable Bit Rate）数据，则可以无延迟地发送UBR连接的单元。 状态报告管理单元（240）在本地存储器的状态队列的循环位置记录状态信息，并且当调度和分割单元（210）与状态报告信息一起发送状态报告请求信号时中断主机CPU。
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