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公开(公告)号：KR1020140059700A
公开(公告)日：2014-05-16
申请号：KR1020130093677
申请日：2013-08-07
Applicant: 한국전자통신연구원
IPC: H04L12/937 , H04L12/851
CPC classification number: H04L47/2441 , H04L47/2483
Abstract: Provided in an embodiment is a flow switch comprising: a virtual flow recognizing switch part for receiving multiple packets from a hypervisor via a network interface and processing the packets; a flow determining part for extracting flow information corresponding to each packet and determining whether there exists stored previous flow information matched with the flow information; and a packet processing controller for checking whether the flow information is affiliated to set QoS restriction information in the case that there exists the previous flow information, applying previous QoS policy information matched with the previous flow information and controlling the virtual flow recognition switch part to process the corresponding packet from which the flow information is extracted in the case that the flow information is affiliated to the QoS restriction information, and not applying the previous policy information and controlling the virtual flow recognition switch part to the process the corresponding packet in the case that the flow information is not affiliated to the QoS restriction information.
Abstract translation: 在一个实施例中提供了一种流量交换机，包括：虚拟流识别切换部分，用于经由网络接口从管理程序接收多个分组并处理分组; 流量确定部分，用于提取与每个分组相对应的流信息，并确定是否存在与流信息匹配的存储的先前流信息; 以及分组处理控制器，用于在存在先前流信息的情况下检查流信息是否附属于设置QoS限制信息，应用与先前流信息匹配的先前QoS策略信息并控制虚拟流识别切换部分进行处理 在流量信息附属于QoS限制信息的情况下从其中提取流信息的相应分组，并且不应用先前策略信息并且在将虚拟流识别切换部分控制到处理对应的分组的情况下 流量信息不隶属于QoS限制信息。
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公开(公告)号：KR1020120004087A
公开(公告)日：2012-01-12
申请号：KR1020100064750
申请日：2010-07-06
Applicant: 한국전자통신연구원
CPC classification number: G06F13/1668 , G06F13/1652 , G06F13/20 , G06F15/80
Abstract: PURPOSE: A lock-free memory controller and a multiprocessor system using the lock-free memory controller are provided to process shared data in parallel without a need that each processor uses a locking function, thereby linearly increasing processing performance due to an increase in the number of processors. CONSTITUTION: A memory(610) stores shared data. A processor(620) manages a data block of the memory as one data area. A memory controller(630) provides specific data to the processor by a control signal of the processor. If the control signal is a write command, the memory controller reads data of a write address from the memory, stores the data in a temporary buffer, stores write data in a corresponding bit of the temporary buffer, and stores the data of the temporary buffer in the memory.
Abstract translation: 目的：提供无锁存储器控制器和使用无锁存储器控制器的多处理器系统以并行处理共享数据，而不需要每个处理器使用锁定功能，从而由于数量的增加而线性地增加处理性能 的处理器。 构成：存储器（610）存储共享数据。 处理器（620）将存储器的数据块管理为一个数据区域。 存储器控制器（630）通过处理器的控制信号向处理器提供特定的数据。 如果控制信号是写入命令，则存储器控制器从存储器读取写入地址的数据，将数据存储在临时缓冲器中，将写入数据存储在临时缓冲器的相应位中，并存储临时缓冲器的数据 在记忆中
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33.发明公开
公开(公告)号：KR1020110123102A
公开(公告)日：2011-11-14
申请号：KR1020100042569
申请日：2010-05-06
Applicant: 한국전자통신연구원
IPC: H01L31/04
CPC classification number: H01G9/2068 , H01G9/2031 , H01G9/2059 , H01G9/209 , Y02E10/542 , Y02P70/521
Abstract: PURPOSE: A dye sensitized solar cell with a macromolecular film having a mirroring property is provided to easily use light which is thrown out passing through a cell by attaching a macromolecular film with a mirroring property in the back side of a counter electrode. CONSTITUTION: A counter electrode(20) is arranged by facing a working electrode(10). An electrolyte(30) is placed between the working electrode and the counter electrode. A macromolecular film(40) with a mirroring property is attached to the back side of the counter electrode. A metal oxide particle layer(12) is formed on a conductive substrate(11). A dye material is adsorbed in and adhered to the metal oxide particle layer.
Abstract translation: 目的：提供具有镜面特性的高分子膜的染料敏化太阳能电池，以容易地使用通过在反电极背面附着具有镜像性的高分子膜而通过电池的光。 构成：对置电极（20）通过面对工作电极（10）而布置。 电解质（30）被放置在工作电极和对电极之间。 具有镜面特性的高分子膜（40）附着在对电极的背面。 在导电性基板（11）上形成金属氧化物粒子层（12）。 染料材料被吸附并附着在金属氧化物颗粒层上。
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公开(公告)号：KR1020110049636A
公开(公告)日：2011-05-12
申请号：KR1020100039211
申请日：2010-04-27
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A multi-layer parallel processing device and method thereof are provided to solve a locality problem which can be a problem in parallel processing. CONSTITUTION: A layer parallel processor(21,22) processes flow data corresponding to a allocated layer if flow data is inputted. A common database(23) stores a process result of a layer parallel processors. A layer parallel processor is composed of a flow processor(2100), a scheduler(2200), and a multiprocessor arranger(2300). The multiprocessor arranger processes parallel flow data according to a flow type at respectively different processors.
Abstract translation: 目的：提供一种多层并行处理装置及其方法，以解决并行处理中存在的问题的局部性问题。 构成：如果流数据被输入，层并行处理器（21,22）处理对应于所分配层的流数据。 公共数据库（23）存储层并行处理器的处理结果。 层并行处理器由流处理器（2100），调度器（2200）和多处理器编排器（2300）组成。 多处理机整理器根据不同处理器上的流类型处理并行流数据。
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公开(公告)号：KR1020110008615A
公开(公告)日：2011-01-27
申请号：KR1020090066038
申请日：2009-07-20
Applicant: 한국전자통신연구원
IPC: H04L7/08
CPC classification number: H03L7/093 , G04C11/04 , H03L7/099 , H04J3/0667
Abstract: PURPOSE: A time synchronization apparatus based on parallel process is provided to reduce the phase noise by reducing the phase variation of a clock corresponding to the reference clock of a slave device. CONSTITUTION: A time phase detector(210) calculates the difference between local time information and the time information of the slave device. A parallel filter unit(220) comprises a first filter unit and a second filter unit which low-pass filters the signal outputted b the time phase detector. An adder(230) adds up the signal outputted from the first filter unit and the second filter unit of the parallel filter unit.
Abstract translation: 目的：提供一种基于并行处理的时间同步装置，通过减少与从设备的参考时钟相对应的时钟的相位变化来减小相位噪声。 构成：时间相位检测器（210）计算本地时间信息与从设备的时间信息之间的差异。 并行滤波器单元（220）包括第一滤波器单元和对时间相位检测器输出的信号进行低通滤波的第二滤波器单元。 加法器（230）将从第一滤波器单元输出的信号和并行滤波器单元的第二滤波器单元相加。
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Patent Agency Ranking
公开(公告)号：KR1020110007028A
公开(公告)日：2011-01-21
申请号：KR1020100036620
申请日：2010-04-20
Applicant: 한국전자통신연구원
IPC: H04L7/02
CPC classification number: H04J3/0697 , H04J3/0644
Abstract: PURPOSE: A time stamping apparatus and a method for accurate synchronization in network timing are provided to implement accurate synchronization by accurately measuring a time of transmitting data and a time of receiving data. CONSTITUTION: A synchronous pulse signal generator(110) generates a pulse signal synchronized with a local clock of a data receiving unit from received data. A receiving time measuring unit(120) measures a time stamp value of a time of receiving data by using the pulse signal. A synchronous pulse signal generator is formed in a physical layer of a receiving unit. The receiving time measuring unit is arranged in an higher layer than the physical layer of the receiving unit.
Abstract translation: 目的：提供时间戳设备和网络定时精确同步的方法，通过精确测量发送数据的时间和接收数据的时间来实现准确的同步。 构成：同步脉冲信号发生器（110）从接收的数据产生与数据接收单元的本地时钟同步的脉冲信号。 接收时间测量单元（120）通过使用脉冲信号测量接收数据的时间的时间戳值。 在接收单元的物理层中形成同步脉冲信号发生器。 接收时间测量单元布置在比接收单元的物理层更高的层中。
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公开(公告)号：KR1020080052132A
公开(公告)日：2008-06-11
申请号：KR1020070018950
申请日：2007-02-26
Applicant: 한국전자통신연구원
CPC classification number: H04L47/29 , H04L47/2441 , H04L47/32
Abstract: A band control switch and a band control method thereof are provided to lower the limited band of each subscriber using a band control switch when the use rate of traffic is higher than a threshold value in an output port and hold the guaranteed band of all subscribers using the band control switch, thereby holding service support only in at least contracted guaranteed band. A grade initializing unit initializes the contract band grade information of a subscriber recorded in a contract band grade table(S510). A traffic load calculator determines whether a buffer threshold value separation state occurs(S520). The traffic load calculator determines a registration subscriber to be a limited band control target when it is determined that the buffer threshold value separation state occurs(S530). The traffic load calculator calculates the traffic load of an output port corresponding to the determined registration subscriber(S540). A grade controller compares the calculated traffic load of the output port with the maximum threshold value and the minimum threshold value and controls the limited band grade information of subscribers passing through the output port(S550,S560). The grade controller reflects the limited band grade information of a subscriber passing through the controlled output port to a band grade table applying a service registered subscriber(S570).
Abstract translation: 提供频带控制开关及其频带控制方法，当业务的使用率高于输出端口的阈值时，使用频带控制开关来降低每个用户的有限频带，并保持所有用户的保证频带使用 频带控制开关，从而仅在至少承包保证频带中保持服务支持。 等级初始化单元初始化记录在合同频带等级表中的用户的合同频段等级信息（S510）。 交通负荷计算器确定是否发生缓冲器阈值分离状态（S520）。 当确定发生缓冲器阈值分离状态时，业务负载计算器确定注册用户为有限频带控制目标（S530）。 业务负载计算器计算与确定的注册用户相对应的输出端口的业务负载（S540）。 等级控制器将输出端口的计算流量负载与最大阈值和最小阈值进行比较，并控制通过输出端口的用户的受限频段等级信息（S550，S560）。 等级控制器将通过受控输出端口的用户的有限频带等级信息反映到应用服务注册用户的频带等级表（S570）。
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公开(公告)号：KR1020070061350A
公开(公告)日：2007-06-13
申请号：KR1020060113472
申请日：2006-11-16
Applicant: 한국전자통신연구원 , 연세대학교 산학협력단
Abstract: An apparatus and a method for restoring a multiple linked clock/data using a phase interpolator are provided to restore input data and a clock of an improved jitter performance by changing a current source weight value corresponding to a core code by a non-linear compensation circuit. An apparatus for restoring a multiple linked clock/data using a phase interpolator(204) includes a phase detection unit(201), a phase combining control unit(202), a non -linear compensation unit(203), and the phase interpolator(204). The phase detection unit(201) calculates a phase difference by comparing a phase of a restoring clock with a phase of input data. The phase combining control unit(202) generates a phase combining control code which is mapped according to the restoring clock and the phase difference. The non-linear compensation unit(203) generates a current source weight value based on a compensation function which is an inverse function of a non-linear function having a factor of the phase combining control code. The phase interpolator(204) selects two reference clocks of multiple phase reference clocks according to the current source weight value, and combines the two selected reference clocks. The phase interpolator(204) generates and outputs a new restoring clock having a linear phase to the phase detection unit(201).
Abstract translation: 提供一种使用相位内插器恢复多个链接的时钟/数据的装置和方法，以通过非线性补偿电路改变对应于核心码的电流源权重值来恢复输入数据和改善的抖动性能的时钟 。 一种使用相位内插器（204）恢复多个链接的时钟/数据的装置，包括相位检测单元（201），相位组合控制单元（202），非线性补偿单元（203）和相位内插器 204）。 相位检测单元（201）通过将恢复时钟的相位与输入数据的相位进行比较来计算相位差。 相位合成控制部（202）生成根据恢复时钟映射的相位合成控制码和相位差。 非线性补偿单元（203）基于作为具有相位合并控制码的因子的非线性函数的反函数的补偿函数生成电流源权重值。 相位插值器（204）根据当前的源权重值选择多个相位基准时钟的两个参考时钟，并组合两个所选择的参考时钟。 相位插值器（204）产生并向相位检测单元（201）输出具有线性相位的新的恢复时钟。
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公开(公告)号：KR101544972B1
公开(公告)日：2015-08-18
申请号：KR1020090118602
申请日：2009-12-02
Applicant: 한국전자통신연구원
Abstract: 병목현상을방지할수 있는네트워크패킷처리장치및 방법을개시한다. 본발명의병목현상방지용네트워크패킷처리장치는수신된네트워크패킷원본을임시저장하는패킷버퍼와, 상기임시저장된원본에대한사본패킷의데이터패턴을검사하여상기원본네트워크패킷의처리와관련된처리규칙을생성하는적어도하나의패킷검사부와, 상기생성된처리규칙을저장하는규칙저장부와, 상기규칙저장부에저장된처리규칙에따라상기패킷버퍼에저장된원본네트워크패킷을처리하는패킷처리부를포함한다. 이에따라네트워크패킷처리시의병목현상을방지하고네트워크패킷의검사및 처리효율을향상시킬수 있다.
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