公开(公告)号：EP1417540A2

公开(公告)日：2004-05-12

申请号：EP02704323.1

申请日：2002-01-31

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SINGH, Bhanwar ,  TEMPLETON, Michael, K.,c/o IMT ,  RANGARAJAN, Bharath ,  SUBRAMANIAN, Ramkumar

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/70675

Abstract: A system for monitoring a latent image exposed in a photo resist (300, 310, 675, 790) during semiconductor manufacture is provided. The system includes one or more light sources (110, 635, 740), each light source (110, 635, 740) directing light (760, 1602, 1712, 1840, 1940, 2040) to the latent image and/or one or more gratings exposed on one or more portions of a wafer (160, 400, 540, 665, 910, 1204, 1820, 1920, 2020). Light reflected (770, 1604, 1714, 1842, 1942, 2042) from the latent image and/or the gratings is collected by a signature system (630, 720), which processes the collected light. Light passing through the latent image and/or gratings may similarly be collected by the signature system (630, 720), which processes the collected light. The collected light is analyzed and can be employed to generate feedback information to control the exposure. The collect light is further analyzed and can be employed to generate feed forward information that can be employed to control post exposure processes including development and baking processes.

公开(公告)号：EP1290496B1

公开(公告)日：2003-12-10

申请号：EP01930611.7

申请日：2001-04-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SUBRAMANIAN, Ramkumar ,  PHAN, Khoi, A. ,  SINGH, Bhanwar ,  RANGARAJAN, Bharath

IPC: G03F1/14

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70441

公开(公告)号：EP1290496A2

公开(公告)日：2003-03-12

申请号：EP01930611.7

申请日：2001-04-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SUBRAMANIAN, Ramkumar ,  PHAN, Khoi, A. ,  SINGH, Bhanwar ,  RANGARAJAN, Bharath

IPC: G03F1/14

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70441

Abstract: The present invention relates to a system and method of modifying (660) mask layout data (100) to improve the fidelity of mask manufacture. The system and method include determining (645, 650, 655) the difference between the mask layout design (100) and the mask features (20) as written, and generating sizing corrections (160). The sizing corrections (160) can be used to modify (660) the mask layout data (100), and/or stored in a database (170).

公开(公告)号：EP1527478A1

公开(公告)日：2005-05-04

申请号：EP03766836.5

申请日：2003-07-03

Applicant: Advanced Micro Devices, Inc.

Inventor： SUBRAMANIAN, Ramkumar ,  LYONS, Christopher, F.

IPC: H01L21/768 ,  H01L21/66

CPC classification number: H01L21/76807 ,  H01L21/76813 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are methods of dual damascene processing, involving forming a plurality of via openings in the insulation structure containing a single layer of a dielectric material; and simultaneously (i) forming a plurality of trenches in the insulation structure, each trench positioned along the substantially straight line of a group of via openings, and (ii) monitoring the formation of trenches using a scatterometry system to determine trench depth, and terminating forming the trenches when a desired trench depth is attained.

Abstract translation: 公开了双镶嵌处理​​的方法，涉及在包含单层介电材料的绝缘结构中形成多个通孔开口; 同时（i）在绝缘结构中形成多个沟槽，每个沟槽沿着一组通道开口的基本上直线定位，以及（ii）使用散射测量系统监测沟槽的形成以确定沟槽深度，并且终止 当达到期望的沟槽深度时形成沟槽。

公开(公告)号：EP1336193A2

公开(公告)日：2003-08-20

申请号：EP01997211.6

申请日：2001-10-30

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： LYONS, Christopher, F. ,  SUBRAMANIAN, Ramkumar ,  PLAT, Marina, V. ,  LUKANC, Todd, P.

IPC: H01L21/027

CPC classification number: H01L21/31144

Abstract: A method of forming a small contact hole (160) uses a bright field mask (130) to form a small cylinder (140) in a positive resist layer (120) after exposure and developing. A negative resist layer (150) is formed around the small cylinder, and then etched or polished back to leave a top portion of the small cylinder exposed above the negative resist layer. The negative resist layer and the small cylinder (positive resist) are flood exposed to light, and then subject to a developer. What remains is a small contact hole (160) located where the small cylinder was previously located.

公开(公告)号：EP1295311A1

公开(公告)日：2003-03-26

申请号：EP01931007.7

申请日：2001-05-01

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SUBRAMANIAN, Ramkumar ,  TEMPLETON, Michael, K. ,  RANGARAJAN, Bharath

IPC: H01L21/00

CPC classification number: H01L21/67115

Abstract: A system, (20) for regulating heating temperature of a material is provided. The material may be a photoresist (22), a top or bottom anti-reflective coating, a low K dielectric material, SOG or other spin-on material, for example. The system (20) includes a plurality of lamps (40) and optical fibers (44) directing radiation to and heating a respective portions of a bakeplate (30) on which the material is to be placed. In one embodiment, the temperature at various locations on the material placed on the bakeplate (30) is determined and the heating rates are controlled in response to those measurements. In another aspect of the invention, the temperature at various portions of the bakeplate (30) is determined and controlled. In this latter aspect, uniform heating of the material is a consequence of uniform bakeplate (30) temperature.

公开(公告)号：EP1264340A2

公开(公告)日：2002-12-11

申请号：EP01922242.1

申请日：2001-02-21

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SUBRAMANIAN, Ramkumar ,  YANG, Wenge

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76895 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/3127 ,  H01L21/76802 ,  H01L21/76834

Abstract: The present invention relates to a methodology of fabricating a local interconnect. The methodology includes the steps of forming an organic stop layer over a semiconductor structure having at least one conductive region, forming an insulating layer over the organic layer, forming a photoresist layer over the insulating layer, patterning the photoresist layer with at least one opening above the at least one conductive region, etching at least one opening in the insulating layer, concurrently stripping the photoresist layer and an exposed portion of the organic layer and filling the at least one opening with a conductive material to form the local interconnect.

公开(公告)号：EP1554750A2

公开(公告)日：2005-07-20

申请号：EP03776412.3

申请日：2003-10-14

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CHOO, Bryan, K. ,  SINGH, Bhanwar ,  SUBRAMANIAN, Ramkumar ,  RANGARAJAN, Bharath

IPC: H01L21/66

CPC classification number: H01L22/20 ,  G01N21/4738 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.

Abstract translation: 公开了一种用于监视和控制半导体制造工艺的系统和方法。 根据基于散射测量的技术进行测量，在晶片经历制造过程时在晶片上演变的电路结构中重复进行。 该测量结果可用于生成前馈和/或反馈控制数据，该数据可用于选择性地调整一个或多个制造部件和/或与其相关的操作参数以适应制造过程。 另外，例如，可以基于成本效益分析来采用测量来确定是否丢弃晶圆或其部分。 电路结构中的直接测量减少了牺牲有价值的芯片面积，因为可能不需要在晶片内形成测试光栅结构，并且还便于控制实际影响所得芯片性能的元件。

公开(公告)号：EP1279072B1

公开(公告)日：2004-10-06

申请号：EP01927263.2

申请日：2001-04-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： RANGARAJAN, Bharath ,  SUBRAMANIAN, Ramkumar ,  PHAN, Khoi, A. ,  SINGH, Bhanwar ,  TEMPLETON, Michael, K. ,  YEDUR, Sanjay, K. ,  CHOO, Bryan, K.

IPC: G03F7/40 ,  G03F7/26

CPC classification number: G03F7/265 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

Abstract: In one embodiment, the present invention relates to a method of processing an ultra-thin resist (16), involving the steps of depositing the ultra-thin resist (16) over a semiconductor substrate (12), the ultra-thin resist (16) having a thickness less than about 3,000 ANGSTROM ; irradiating the ultra-thin resist (16) with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin resist (16); and contacting the ultra-thin resist (16) with a silicon containing compound in an environment of at least one of ultraviolet light and ozone, wherein contact of the ultra-thin resist (16) with the silicon containing compound is conducted between irradiating and developing the utra-thin resist (16) or after developing the ultra-thin resist (16).

公开(公告)号：EP1402242A2

公开(公告)日：2004-03-31

申请号：EP02707668.6

申请日：2002-01-31

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SUBRAMANIAN, Ramkumar ,  RANGARAJAN, Bharath ,  SINGH, Bhanwar ,  TEMPLETON, Michael, K.

IPC: G01N21/47 ,  H01L21/66

CPC classification number: H01L21/7681 ,  G01N21/4738 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67253 ,  H01L22/12

Abstract: A system (1000) for characterizing an etch process, such as forming a dual damascene structure, via scatterometry based real time imaging is provided. The system (1000) includes one or more light sources (1020), each light source directing light to one or more features and/or gratings (1015) on a wafer (1010). Light reflected from the features and/or gratings (1015) is collected by a measuring system (1070), which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer (1010). The measuring system (1070) provides etching related data to a processor (1040) that determines the desirability of the etching of the respective portions of the wafer (1010). The system (1000) also includes one or more etching devices (1030), each such device corresponding to a portion of the wafer (1010) and providing for the etching thereof. The processor (1040) produces a real time etch image to characterize the progress of the etching and, in one example, produces suggested adaptations to the etch process.