公开(公告)号：WO1997022061A1

公开(公告)日：1997-06-19

申请号：PCT/US1996019321

申请日：1996-12-05

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  HURRELL, Christopher, Peter

IPC: G06F17/10

CPC classification number: H03H17/0664

Abstract: Gain correction for a digital filter is accomplished by using: a multiplier (24b) for multiplying each data value by a coefficient representing the impulse response of the filter to form a convolution of the data values; and an accumulator (26b) for accumulating the sum of the product of each multiplication to obtain a complete convolution. Further, the gain correction for the digital filter is accomplished by determining the difference between the positive full scale output and the negative full scale output of the filter; combining this difference with the ideal full scale output value to obtain the gain error factor; dividing the gain error factor by the full scale ideal value to obtain the gain correction factor; multiplying the negated accumulated sum of the product of each multiplication by the gain correction factor to obtain the gain error adjustment and combining the gain error adjustment factor with the accumulated sum to compensate for gain errors in the filter output.

Abstract translation: 数字滤波器的增益校正通过使用：乘法器（24b），用于将每个数据值乘以表示滤波器的脉冲响应的系数，以形成数据值的卷积; 以及累加器（26b），用于累积每个乘法乘积的和以获得完整的卷积。 此外，数字滤波器的增益校正通过确定滤波器的正满量程输出和负满量程输出之间的差异来实现; 将该差异与理想的满量程输出值组合以获得增益误差因子; 将增益误差因子除以满量程理想值以获得增益校正因子; 将乘法乘积的乘积累积乘以增益校正因子以获得增益误差调整，并将增益误差调整因子与累加和组合，以补偿滤波器输出中的增益误差。

公开(公告)号：WO1997013326A1

公开(公告)日：1997-04-10

申请号：PCT/US1996015407

申请日：1996-09-26

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  COHN, Michael, C., W. ,  Wynne, John, M.

IPC: H03M01/70

CPC classification number: H03M1/70 ,  G06F5/00 ,  G08C19/02

Abstract: An apparatus and a method for controlling a mode of operation of a data converter is based on a length of an input word signal to the data converter. The apparatus includes a bit counter that counts the number of bits in the word received by the data converter and provides a word length signal corresponding to the number of bits in the word, and a mode selector that receives the word length signal and selects an operational mode of the data converter based on the word length signal. The method includes steps of counting the number of bits in the word, and selecting a mode of operation of the data converter based on the number of bits in the word.

Abstract translation: 用于控制数据转换器的操作模式的装置和方法基于到数据转换器的输入字信号的长度。 该装置包括对由数据转换器接收的字中的位数进行计数的位计数器，并提供对应于字中的位数的字长信号，以及模式选择器，其接收字长信号并选择操作 数据转换器的模式基于字长信号。 该方法包括以下步骤：对单词中的位数进行计数，并且基于单词中的位数选择数据转换器的操作模式。

公开(公告)号：WO1997013325A1

公开(公告)日：1997-04-10

申请号：PCT/US1996015812

申请日：1996-10-02

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  ADAMS, Robert, W. ,  KWAN, Tom, W.

IPC: H03L07/18

CPC classification number: H03L7/1806 ,  H03H17/06 ,  H03H17/0614 ,  H03H17/0657

Abstract: A digital oversampling noise-shaping system includes a digital noise-shaped clock signal generating circuit, including a digitally controlled oscillator (DCO) operating at a fixed master clock rate, that receives a digital input sample clock signal having an input sample rate and produces a noise-shaped clock signal having a variable rate with an average rate equal to a multiple of the input sample rate. In one embodiment, an interpolator is coupled to the clock signal generating circuit and receives the digital input samples at an input sample rate and, responsive to the noise-shaped clock signal, upsamples the digital input samples at the variable rate. A hold circuit repeats the interpolated samples at the master clock rate. A digital noise-shaping circuit, coupled to the hold circuit, performs digital noise-shaping on the repeated samples received from the hold circuit. In another embodiment, a decimator is coupled to the clock signal generating circuit. Digital input samples having an input sample rate are latched to the input of the decimator at a rate controlled by the noise-shaped clock signal. The clock signal generating circuit includes a phase locked loop (PLL) in one embodiment. The digital noise-shaping circuit, in one embodiment, includes sigma-delta modulator in which the downstream one of first and second integrators operates at a reduced multiple of a fixed master clock rate.

Abstract translation: 数字过采样噪声整形系统包括数字噪声形状的时钟信号发生电路，其包括以固定的主时钟速率工作的数字控制振荡器（DCO），其接收具有输入采样率的数字输入采样时钟信号，并产生一个 噪声形状的时钟信号具有平均速率等于输入采样率的倍数的可变速率。 在一个实施例中，内插器耦合到时钟信号发生电路，并以输入采样率接收数字输入采样，并响应于噪声形状的时钟信号以可变速率对数字输入采样进行上采样。 保持电路以主时钟速率重复插值样本。 耦合到保持电路的数字噪声整形电路对从保持电路接收的重复样本执行数字噪声整形。 在另一个实施例中，抽取器耦合到时钟信号发生电路。 具有输入采样率的数字输入样本以噪声形状的时钟信号控制的速率被锁存到抽取器的输入端。 时钟信号发生电路在一个实施例中包括锁相环（PLL）。 在一个实施例中，数字噪声整形电路包括Σ-Δ调制器，其中第一和第二积分器中的下游一个以固定主时钟速率的减少的倍数工作。

公开(公告)号：WO1997012398A1

公开(公告)日：1997-04-03

申请号：PCT/US1996013543

申请日：1996-08-23

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  PENCHUK, Robert, A.

IPC: H01L23/495

CPC classification number: H01L24/32 ,  H01L23/4334 ,  H01L23/49589 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04026 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: An integrated circuit assembly (10) is formed with an integral power supply decoupling capacitor for monolithic circuitry in a semiconductor substrate (12) by using the substrate itself as one plate of the capacitor. A dielectric (14) is formed on the "back" side, or surface, of the substrate (12) (i.e., the surface opposite the surface in which component structures are formed) such as by growing a native oxide thereon. Using a conductive epoxy (16), the back side of the substrate (12) (actually, the dielectric layer thereon) is then attached to a conductive foundation member (18), which forms the other plate of the capacitor when a potential is applied across the substrate (12) and the foundation member (18). The conductive foundation member (18, 22) also may be connected to a heat sink structure (22) integral with the package (29). The heat sink (22) may extend through a window in the package (29) providing a path and surface via which heat may be tranferred to an external heat sink if a larger heat sink mass is needed. For safety, the heat sinks (22) and the die attach paddle (18) may be maintained at a suitable potential, such as ground, while the substrate (12) can be at another supply potential.

Abstract translation: 集成电路组件（10）通过使用衬底本身作为电容器的一个板，在半导体衬底（12）中形成有用于单片电路的整体电源去耦电容器。 电介质（14）形成在衬底（12）的“背面”或表面上（即，与其形成部件结构的表面相对的表面），例如通过在其上生长天然氧化物。 使用导电环氧树脂（16），然后将衬底（12）的背面（实际上是其上的电介质层）附着到导电基底构件（18），当施加电位时，形成电容器的另一个板 穿过基底（12）和基础构件（18）。 导电基础构件（18,22）也可以连接到与封装（29）成一体的散热器结构（22）。 散热器（22）可以延伸穿过包装（29）中的窗口，提供路径和表面，如果需要较大的散热器质量，则可以将热量传递到外部散热器。 为了安全起见，当衬底（12）可以处于另一供电电位时，散热器（22）和管芯附接板（18）可以保持在合适的电势，例如接地。

公开(公告)号：WO1996041419A1

公开(公告)日：1996-12-19

申请号：PCT/US1996008533

申请日：1996-06-04

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  ADAMS, Robert, W.

IPC: H03L07/099

CPC classification number: H03L7/0994 ,  G06F1/025

Abstract: A digitally controlled oscillator in a digital phase-locked loop provides an additional output signal which indicates the time difference between clock pulses output from the digitally controlled oscillator and clock pulses of an ideal clock signal of the same average frequency. This additional signal is called a residue signal. This residue signal may then be used to extrapolate or interpolate outputs of continuously variable interpolation or decimation filters using the output clock signal of the digital phase-locked loop generated according to the digitally controlled oscillator. Because the residue signal may be used in interpolation or decimation filters, it is also applicable to analog-to-digital converters, digital-to-analog converters and sample rate converters which use such filters. The digital phase-locked loop circuit is simpler than previous circuits because a conventional overflowing accumulator may be used, which is a first order system, rather than a higher order multi-bit noise shaper. Additionally, a simpler interpolation or decimation filter may be used.

Abstract translation: 数字锁相环中的数字控制振荡器提供附加的输出信号，其指示从数字控制振荡器输出的时钟脉冲与相同平均频率的理想时钟信号的时钟脉冲之间的时间差。 该附加信号称为残留信号。 然后可以使用该残留信号来使用根据数字控制的振荡器产生的数字锁相环的输出时钟信号来推断或内插连续可变内插或抽取滤波器的输出。 由于残留信号可用于插值或抽取滤波器，因此也适用于使用这种滤波器的模数转换器，数模转换器和采样率转换器。 数字锁相环电路比以前的电路简单，因为可以使用作为一阶系统的常规溢出累加器，而不是高阶多位噪声整形器。 此外，可以使用更简单的内插或抽取滤波器。

公开(公告)号：WO1996039632A1

公开(公告)日：1996-12-12

申请号：PCT/US1996008708

申请日：1996-06-05

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MARTIN, John, R. ,  ROBERTS, Carl, M., Jr.

IPC: G01P01/02

CPC classification number: G01P1/023 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A die (10, 70) has a part that is sealed with a cap (30, 50, 80). The seal (32, 52, 84) can be hermetic or non-hermetic. If hermetic, a layer (74) of glass or metal is formed in the surface of the die (10, 70), and the cap (80) has a layer (84) of glass or metal at a peripheral area so that, when heated, the layers (74, 84) form a hermetic seal. A non-hermetic seal can be formed by bonding a cap (30, 50) with a patterned adhesive (32, 52). The cap (30, 50, 80), which can be silicon or can be a metal paddle, is electrically coupled to a fixed voltage to shield the part of the die (10, 70).

Abstract translation: 模具（10,70）具有用盖（30,50,80）密封的部分。 密封件（32,52,84）可以是密封的或非密封的。 如果密封，则在模具（10,70）的表面中形成玻璃或金属层（74），并且帽（80）在周边区域具有玻璃或金属层（84），使得当 加热，层（74,84）形成气密密封。 可以通过将盖（30,50）与图案化的粘合剂（32,52）结合来形成非气密密封。 可以是硅或可以是金属焊盘的盖（30,50,80）电耦合到固定电压以屏蔽模具（10,70）的部分。

公开(公告)号：WO1996039614A3

公开(公告)日：1996-12-12

申请号：PCT/US1996008707

申请日：1996-06-05

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GEEN, John, A.

IPC: G01C19/56

公开(公告)号：WO1996037953A1

公开(公告)日：1996-11-28

申请号：PCT/US1996007579

申请日：1996-05-23

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  LEE, Wai, L. ,  KWAN, Tom, W.

IPC: H03H17/04

CPC classification number: H03H17/0444 ,  H03H17/045 ,  H03H19/004

Abstract: A digital filtering method that includes sampling an input signal at a first rate, integrating the signal, sampling the integrated version at a different rate, and combining the sampled integrated version with the input signal. The method can include again integrating the integrated version, sampling the twice integrated version at a third rate different from the first and second rates, and combining the twice integrated version with the integrated version and the input signal. The integrated version can be again integrated, the twice integrated version can be sampled at a third rate different from the first and second rates, and the twice integrated version can be combined with the integrated version. A common circuit component can be multiplexed to participate in two integrating steps.

Abstract translation: 一种数字滤波方法，其包括以第一速率对输入信号进行采样，对信号进行积分，以不同速率对集成版本进行采样，以及将采​​样的集成版本与输入信号进行组合。 该方法可以包括再次集成集成版本，以与第一和第二速率不同的第三速率对两次集成版本进行采样，并将两次集成版本与集成版本和输入信号组合。 集成版本可以再次集成，可以以与第一和第二速率不同的第三速率对两次集成版本进行采样，并且两次集成版本可以与集成版本组合。 公共电路组件可以被多路复用以参与两个集成步骤。

公开(公告)号：WO1996031944A1

公开(公告)日：1996-10-10

申请号：PCT/US1996004685

申请日：1996-04-05

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  LEE, Wai, L. ,  GRANT, Norman, D. ,  FERGUSON, Paul, F., Jr.

IPC: H03D07/16

CPC classification number: H03D7/165

Abstract: A circuit that provides samples of in-phase and quadrature componenents of an input waveform includes an oversampling sigma-delta ADC that receives the input waveform and converts the input waveform to digital samples at an oversampling rate. A first digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the in-phase component samples of the input waveform. A second digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the quadrature component samples of the input waveform.

Abstract translation: 提供输入波形的同相和正交分量样本的电路包括过采样Σ-ΔADC，其接收输入波形，并以过采样速率将输入波形转换为数字采样。 耦合到ADC的第一个数字滤波器从ADC接收数字采样，并提供输入波形的同相分量采样。 耦合到ADC的第二个数字滤波器从ADC接收数字采样，并提供输入波形的正交分量采样。

公开(公告)号：WO1996022632A1

公开(公告)日：1996-07-25

申请号：PCT/US1996000698

申请日：1996-01-18

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GARAVAN, Patrick, J. ,  BYRNE, Eanonn

IPC: H03M01/10

CPC classification number: H03M1/002 ,  H03M1/1009 ,  H03M1/46 ,  H03M1/804

Abstract: Using a power-up delay circuit on an analog/digital converter integrated circuit (i.e., an analog-to-digital converter or a digital-to-analog converter) to generate a signal delayed from power-up, and initiating a calibration of the converter upon detecting the delayed signal. In preferred embodiments, calibration can also be initiated in response to a signal on a calibration input pin of the integrated circuit, and the duration of the delay can be derived from a reference (e.g., by charging an external capacitor with it) or from the duration of a calibration operation. Circuitry can be provided to automatically place the circuit in an operating mode upon power-up that keeps the integrated circuit in shutdown mode when it is not converting or calibrating.

Abstract translation: 使用模拟/数字转换器集成电路（即，模数转换器或数模转换器）上的上电延迟电路来产生从上电延迟的信号，并启动校准 转换器检测延迟信号。 在优选实施例中，也可以响应于集成电路的校准输入引脚上的信号来启动校准，并且延迟的持续时间可以从参考（例如，通过用它对外部电容器充电）或从 校准操作的持续时间。 可以提供电路，以在上电时自动将电路置于工作模式，当集成电路不进行转换或校准时，可将集成电路保持在关断模式。