Abstract:
A display may have an array of pixels. A transparent conductive layer may serve as a common voltage electrode layer and may distribute a common voltage to each of the pixels. Metal layers may be used to form routing structures. One of the metal layers may be patterned to form gate lines that distribute control signals to thin-film transistors in the pixels. Touch sensor circuitry may be coupled to horizontal and vertical capacitive touch sensor electrodes formed from the transparent conductive layer. A touch sensor signal border routing path in an inactive area of the display may have openings that run parallel to the gate lines and that each overlap one of the gate lines to reduce capacitive coupling between the gate lines and the touch sensor signal border routing path.
Abstract:
A display may have an array of pixels that forms an active display area for displaying images. An inactive border area of the display may have contact pads to which integrated circuits and flexible printed circuits may be attached. The contact pads may be free of organic planarization layers and may be formed from multiple stacked conductive layers. The inactive portion of the display may include electrostatic discharge protection structures associated with the pads, metal layers that form signal paths extending between the pads and the pixels, interlayer dielectric layers for protecting the metal layers that form the signal paths, polysilicon footer structures that help prevent undercutting of gate insulator material in the vicinity of the pads, and other pad and signal line structures.
Abstract:
A display may have an array of pixels. The array of pixels may have a shape such as a circular shape or other shape with a curved edge. Display driver circuitry may supply data signals to the pixels using folded vertical data lines and bisected horizontal gate lines. Each folded vertical lines may have a first segment in a left half of the array and a second segment in a right half of the display. Curved coupling segments in an inactive area of the display may be used in joining the first and second segments. Display driver circuits may be provided in top and bottom portions of the inactive area to supply data to respective top and bottom portions of the array. Gate driver output buffers may have different strengths in different rows of the array.
Abstract:
A display may have an array of pixels. The pixels may have color filter elements such as red, green, and blue color filter elements. A layer of opaque material may be used to form a black matrix. The black matrix may have openings that receive the color filter elements. A backlight unit may produce backlight illumination for the display. A reflector layer may be interposed between the black matrix and the backlight unit. The reflector layer may have openings aligned with the openings in the black matrix and the color filter elements and may overlap the black matrix. Some of the backlight from the backlight unit may pass through the color filter elements. Other backlight may by be recycled by being reflected off of the reflector layer, thereby enhancing backlight efficiency.
Abstract:
Systems including and methods for forming a backplane for an electronic display are presented. The backplane includes interlaced crystallized regions, and the interlaced crystallized regions include at least a left column of crystallized regions and a right column of crystallized regions. The left and right columns include rows of crystallized regions with gaps disposed between each of the rows. Furthermore, each crystallized region in the left column extends into a corresponding gap in the right column, and each crystallized region in the right column extends into a corresponding gap in the left column.
Abstract:
A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. A passivation layer may be formed on the thin-film transistor layers. An oxide liner may be formed on the passivation layer. A first low-k dielectric layer may be formed on the oxide liner. A second low-k dielectric layer may be formed on the first low-k dielectric layer. A common voltage electrode and associated storage capacitance may be formed on the second low-k dielectric layer. Thin-film transistor gate structures may be formed in the passivation layer. Conductive routing structures may be formed on the oxide liner, on the first low-k dielectric layer, and on the second low-k dielectric layer. The use of routing structures on the oxide liner reduces overall routing resistance and enables interlaced metal routing, which can help reduce the inactive border area outside the active display regions.