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公开(公告)号：JPH08286634A
公开(公告)日：1996-11-01
申请号：JP9083395
申请日：1995-04-17
Applicant: FUJITSU LTD
Inventor： ISHIDA KATSUHIRO , UEDA TOSHIO , TAJIMA MASAYA
IPC: H04N5/66 , G06T5/00 , G09G3/20 , G09G3/28 , G09G3/296 , G09G5/37 , H04N1/405 , H04N1/41 , H04N5/70 , H04N9/30
Abstract: PURPOSE: To suppress the occurrence of a flicker or a disagreeable fixed pattern, etc., in all displays and to prevent the deterioration in video quality of an image by inserting a different dither pattern into the halftone image data at a gradation selecting time. CONSTITUTION: The halftone image data constituted in image are inputted, and the dither pattern properly selected from a dither pattern generation means 3 is inserted into the inputted halftone image data Din in a proper addition means 2. Thereafter, when error diffusion processing by an error diffusion method is executed in an error diffusion processing part 1, the optional dither pattern is inserted into the halftone image data Din according to the inputted halftone image data Din . Thus, in a halftone display of a matrix panel displaying a digital signal as it is, e.g. a plasma display panel, multi-level is realized in all displays, and the deterioration in the video quality such as the flicker or the disagreeable fixed pattern, etc., caused by the multi-level is suppressed.
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公开(公告)号：JPH08265170A
公开(公告)日：1996-10-11
申请号：JP6018795
申请日：1995-03-20
Applicant: FUJITSU LTD
Inventor： YAMAMOTO AKIRA , TANAHASHI RIKURO , UEDA TOSHIO , KURIYAMA HIROHITO
Abstract: PURPOSE: To materialize the circuit technology suitable for circuit integration by using a synchronizing signal and a signal synchronously with the synchronization of one line of a received serial data string so as to regulate the shift operation thereby generating a required synchronizing signal without the use of a delay circuit. CONSTITUTION: Each bit of an input serial data string is incorporated into an S/P 1 in order synchronizing with a clock signal CKI and outputted in parallel while being collected by n-bit each. Each bit form the S/P 1 is latched in an LT 3 in a rising timing of a synchronizing signal CKE outputted from a DEV 2 and outputted to an X driver 4 as display data in the unit of n-bit from the LT 3. A synchronizing signal XCK' generated by a synchronizing signal generating means 20 includes the synchronizing signal CKE itself or a signal synchronously with it and includes a signal synchronized with the synchronization of one line of the received data string. The signal XLT is generated by a shift circuit 21.
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公开(公告)号：JPH04284489A
公开(公告)日：1992-10-09
申请号：JP4844591
申请日：1991-03-13
Applicant: FUJITSU LTD
Inventor： KURIYAMA HIROHITO , UEDA TOSHIO
Abstract: PURPOSE:To offer the display driving circuit for the flat display which performs stable operation by reducing radiation noises and ground noises due to the switching of applied pulses. CONSTITUTION:The display driving circuit for the flat display is equipped with capacitive display cells 11 which are arranged in matrix, and an Y-side driver circuit 12 which drives the Y electrodes of the flat display and an X-side driver circuit 13 which drives the X electrodes. This display driving circuit has a a control circuit 14 which controls the output of the Y-side driver circuit 12 or X-side driver circuit 13 into a high impedance state when a voltage applied to the driver circuit rises and also applies a high-voltage pulse to the driver circuit driving a counter electrode.
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公开(公告)号：JPH04273288A
公开(公告)日：1992-09-29
申请号：JP3448391
申请日：1991-02-28
Applicant: FUJITSU LTD
Inventor： UEDA TOSHIO , YOSHIKAWA KAZUO , KAMEYAMA SHIGEKI
Abstract: PURPOSE:To offer a PDP driving circuit which can reduce the switching loss of an X-side driver LSI and the charging electric power of a PDP(AC type plasma display panel) and apply an existent driver LSI to a large-capacity, gradational-display PDP as to the low-power driving circuit for the AC type PDP. CONSTITUTION:The PDP driving circuit is equipped with a Y-side driver circuit 12 which drives the rows of the PDP 11 to be driven and an X-side driver circuit 13 which drives the columns of the PDP 11. Further, the circuit has a voltage dividing circuit 15 which outputs a high source voltage Vc for a cancel pulse by dividing a high source voltage Vs for pulse display and a switch 16 which inputs the high source voltage Vs for panel display and high source voltage Vc for the cancel pulse and switches the high supply voltage Vx to the X-side driver circuit 13 to the high source voltage Vc for the cancel pulse in an address period or the high source voltage Vs for panel display in writing or sustaining mode.
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公开(公告)号：JP2003288042A
公开(公告)日：2003-10-10
申请号：JP2003017850
申请日：2003-01-27
Applicant: Fujitsu Ltd , 富士通株式会社
Inventor： YAMAMOTO AKIRA , TAJIMA MASAYA , UEDA TOSHIO , KURIYAMA HIROHITO , ISHIDA KATSUHIRO , KANAZAWA GIICHI
Abstract: PROBLEM TO BE SOLVED: To realize a waveform generating circuit in which waveforms are varied in accordance with the situation.
SOLUTION: The waveform generating circuit is provided with a ROM 651 which stores waveform data related to waveforms and their generation for every cycle and an address generating circuit 74 which successively generates address signals to successively read the waveform data. Moreover, the waveform generating circuit is provided with a skip discriminating circuit 75 which sets a skip address to the circuit 74 when an external instruction signal is inputted to skip reading and the address signal being generated by the circuit 74 becomes a prescribed value and controls the circuit 74 so that it continues the generation operations of the address signal from the skip address.
COPYRIGHT: (C)2004,JPOAbstract translation: 要解决的问题：实现波形发生电路，其中波形根据情况而变化。 解决方案：波形发生电路设有ROM 651，ROM 651存储与每个周期的波形及其产生相关的波形数据，地址产生电路74连续产生地址信号以连续读取波形数据。 此外，波形发生电路设置有跳过识别电路75，当输入外部指令信号以跳过读取并且由电路74产生的地址信号变为规定值时，将跳过地址设置到电路74，并且控制 电路74，从而继续从跳过地址生成地址信号的操作。 版权所有（C）2004，JPO
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Patent Agency Ranking
公开(公告)号：JPH10133623A
公开(公告)日：1998-05-22
申请号：JP28707796
申请日：1996-10-29
Applicant: FUJITSU LTD , MIKOSHIBA SHIGEO
Inventor： MIKOSHIBA SHIGEO , YAMAGUCHI TAKAHIRO , TODA KOSAKU , SHINODA TSUTAE , KARIYA NORIJI , UEDA TOSHIO
Abstract: PROBLEM TO BE SOLVED: To reduce the disorder of a half-tone display as to even a moving picture which is high in moving speed and to improve the moving picture false contour of video by selecting a predetermined light emission block for luminance adjustment, and adding or subtracting the selected light emission block for luminance adjustment to or from a source signal of successive pixels. SOLUTION: The state of an illumination block in a frame or field of two pixels positioned across successive pixels is detected, and the predetermined light emission block for luminance adjustment is selected according to the number of the successive pixels, the state of the two pixels positioned across the successive pixels, and the state of variation between frames or fields of the illumination pattern. Then display data 210 is supplied to a display device 100 through a luminance adjusting light emission block inserting means 200. Here, the inserting means 200 outputs the signal 220 generated by adding or subtracting the light emission block for luminance adjustment to or from the source signal according to whether or not there is variation of the source signal between frames.
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公开(公告)号：JPH1039828A
公开(公告)日：1998-02-13
申请号：JP19891696
申请日：1996-07-29
Applicant: FUJITSU LTD , MIKOSHIBA SHIGEO
Inventor： MIKOSHIBA SHIGEO , YAMAGUCHI TAKAHIRO , TODA KOHSAKU , SHINODA TSUTAE , KARIYA KYOJI , UEDA TOSHIO , ISHIDA KATSUHIRO
Abstract: PROBLEM TO BE SOLVED: To improve the turbulence of a halftone luminance in a picture and the moving picture pseudo contour of a video by adding or subtracting the light emission block for luminance adjustment preliminarily determined to respective pixels according to the state of a change with respect to light emission blocks preliminarily determined to respective pixels in respective frames. SOLUTION: When a dark line is to be generated in the boundary part between halftone levels 128, 127, a stimulus value ΔL(4) by an equivalent pulse (light emission block : subframe) is added. That is, an equivalent pulse EPA is added to the dark line part between the halftone levels 128 and 127 to be generated at the time a display picture is scrolled from the left side to the right side in a state in which the halftone levels 128 and 127 are adjacently displayed. Thus, a stimulus quantity L(x) on retinas is added by the stimulus value ΔL(4) in L(2) of the boundary part between the halftone levels 128 and 127 and the color pseudo coutour (moving picture pseudo contour) of the video is improved.
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公开(公告)号：JPH09212125A
公开(公告)日：1997-08-15
申请号：JP1548996
申请日：1996-01-31
Applicant: FUJITSU LTD
Inventor： YAMAMOTO AKIRA , TAJIMA MASAYA , UEDA TOSHIO , KURIYAMA HIROHITO , ISHIDA KATSUHIRO
Abstract: PROBLEM TO BE SOLVED: To realize a waveform generating circuit which generates complicated waveforms without increasing the amount of ROM data and readout speed. SOLUTION: This circuit is provided with a waveform/control signal ROM 11 which stores the ROM data related to waveforms and their generation, a ROM data readout means 12 which successively reads ROM data stored in the ROM 11, and a ROM data conversion means 13 which successively converts the ROM data read by the ROM data readout means 12 to waveforms. Here, the ROM 11 stores the ROM data divided to the fundamental period data which varies with the fundamental period and the long period data which varies with a long period varying with a period an integer times as long as the fundamental period. The ROM data readout means 12 is so constituted to read the fundamental period data and the long period data with the corresponding periods and the ROM conversion means 13 is so constituted to convert the fundamental period data and the long period data with the corresponding periods.
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公开(公告)号：JPH09185343A
公开(公告)日：1997-07-15
申请号：JP34395395
申请日：1995-12-28
Applicant: FUJITSU LTD
Inventor： TAJIMA MASAYA , UEDA TOSHIO , ISHIDA KATSUHIRO , KURIYAMA HIROHITO
Abstract: PROBLEM TO BE SOLVED: To make frecise gradational display irrelevantly to the difference in display load between subframes by weighting a period of display light emission, subframe by subframe, and making it different for the gradational display. SOLUTION: This device is provided with a data counter 112 as a display load calculating means which calculates the display load of the entire display screen for each subframe and correction period calculating means 110 and 111 which calculates a correction period for the light emission period of a display light emitting means, subframe by subframe, according to the display load of each subframe calculated by the data counter 112 so that the lightness of a display cell by each subframe has a specific ratio between subframes. The display light emitting means emits light for the correction period. The counter 112 is provided with counters as many as the subframes and each counter counts cells where maintained discharging is performed, subframe by subframe, converts the counted value into bit data representing the display load with the ratio to the total number of cells of the entire screen, and outputs the bit data.
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公开(公告)号：JPH09127910A
公开(公告)日：1997-05-16
申请号：JP28297295
申请日：1995-10-31
Applicant: FUJITSU LTD
Inventor： KURIYAMA HIROHITO , TAJIMA MASAYA , UEDA TOSHIO , YAMAMOTO AKIRA , ISHIDA KATSUHIRO
Abstract: PROBLEM TO BE SOLVED: To provide a flat panel display device having high picture quality by providing a conversion table section receiving part of the bit signals of the multi-gradation signal and outputting the superposition conversion output and a synthesis section synthesizing the remaining bit signals and the superposition conversion output signal and generating the sub-frame signal. SOLUTION: Data DT are fed to a conversion table section 322 constituting an LUT via a limit circuit 321. More significant six bits in the outputs RMA 7-RMA0 of the limit circuit 321 are effective, and more significant four bits RMA7-RMA4 among them are fed to the conversion table section 322. The effective more significant four bits among the converted outputs RMD7-RMD0 of the conversion section 322 are outputted as output data Q7-Q4. The less significant four bits RMD3-RMD0 are synthesized by a multiplexer circuit 324 to the outputs S3-S0 shifted with the less significant bits RMA4-RMA0 not subject to conversion by one bit in the less significant direction by a shift circuit 323.
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