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公开(公告)号：DE3584352D1
公开(公告)日：1991-11-14
申请号：DE3584352
申请日：1985-11-20
Applicant: FUJITSU LTD
Inventor： OGAWA JUNJI , TAKEMAE YOSHIHIRO
Abstract: 57 A semiconductor memory device with shift registers used for a video RAM (1), including a memory cell array, bit lines (BL, BL), and word lines (WL), a pair of shift registers (3, 4), and transfer gate circuits (21,22) arranged between the bit lines and the shift registers. Each parallel data transfer circuit is provided between the shift registers for the parallel data transfer between the shift registers, so that high-speed reading and writing of data for a CRT display is realized.
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公开(公告)号：DE3577367D1
公开(公告)日：1990-05-31
申请号：DE3577367
申请日：1985-10-16
Applicant: FUJITSU LTD
Inventor： OGAWA JUNJI
IPC: G11C7/00 , G11C11/401 , G11C11/409 , G11C11/4094 , G11C11/4096 , H01L27/10
Abstract: A semiconductor memory device including a random access memory cell array, a series/parallel data transfer circuit, transfer gate, an active pull-up circuit (1), and an active pull-down circuit (21. The transfer gate is inserted between bit lines of the random access memory cell array and the series/parallel data transfer circuit to carry out parallel transfer of data. Output data of the senes/parallel data transfer circuit is simultaneously written in a group of memory cells of selected work lines by turning on the transfer gate and selection of a word line. When data of each output of steps of the series/parallel data transfer circuit is logic "1", the active pull-up circuit charges up a selected bit line of the random access memory cell array. When data of each output of steps of the series/parallel data transfer circuit is logic "0", the active pull-down circuit discharges a selected bit line of the random access memory cell array. One or more of the active pull-up and active pull-down circuits is arranged in the semiconductor memory device.
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公开(公告)号：DE19758673B4
公开(公告)日：2014-05-22
申请号：DE19758673
申请日：1997-10-09
Applicant: FUJITSU LTD
Inventor： TAMURA HIROTAKA , SAITO MIYOSHI , GOTOH KOHTAROH , WAKAYAMA SHIGETOSHI , OGAWA JUNJI , ARAKI HISAKATSU , CHEUNG TSZ-SHING
IPC: G06F3/00 , G06F13/40 , G06F1/10 , G06F12/00 , G06F13/16 , G06F13/42 , G11C11/401 , G11C11/407 , G11C11/409
Abstract: Empfängerschaltung zur Verwendung in einem Signalübertragungssystem, das Daten über komplementäre Busse (B, /B) überträgt, und das die Daten durch Eliminieren einer Zwischensymbolinterferenzkomponente die von vorhergehenden Daten eingeführt wird, detektiert mit: einem differenziellen Verstärker (2303) mit ersten und zweiten Gateempfangenden komplementären Eingängen, einer Verstärker-Vorladeschaltung (2302), die an jedem der ersten und zweiten Eingänge des differenziellen Verstärkers (2303) vorgesehen ist, um auf eine Weise vorzuladen, die die Empfindlichkeit des differenziellen Verstärkers (2303) erhöht, und zwei Sätzen von ersten und zweiten Kapazitäten, die an den ersten und zweiten Eingängen des differenziellen Verstärkers (2303) vorgesehen sind, wobei die ersten und zweiten Eingänge des differenziellen Verstärkers (2303) mit den komplementären Bussen (B, /B) über die ersten und zweiten Kapazitäten gekoppelt sind, und in jedem Satz von Kapazitäten die erste Kapazität jederzeit mit einem der komplementären Busse (B, /B) gekoppelt ist, wohingegen die zweite Kapazität durch eine Schaltereinheit selektiv mit einem oder dem anderen der komplementären Busse (B, /B) gekoppelt ist, wobei in jedem Satz von Kapazitäten die zweite Kapazität während einem Zwischensymbolinterferenz-Bestimmungsbetriebsschritt durch Anschalten eines Steuersignals (Φ1) an die Schalteinheit mit dem Bus (B, /B) gekoppelt ist, der dem Bus (/B, B) gegenüberliegt, der mit der ersten mit dem gleichen differenziellen Eingang gekoppelten Kapazität gekoppelt ist, und während einem Datenentscheidungsbetriebsschritt durch Anschalten eines zum Steuersignal (Φ1) komplementären Steuersignal (Φ2) an die Schalteinheit mit gleichen Bus (B, /B) gekoppelt ist, der mit der ersten mit dem gleichen differenziellen Eingang gekoppelten Kapazität gekoppelt ist ...
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公开(公告)号：DE69841282D1
公开(公告)日：2009-12-17
申请号：DE69841282
申请日：1998-06-10
Applicant: FUJITSU LTD
Inventor： TAMURA HIROTAKA , ARAKI HISAKATSU , WAKAYAMA SHIGETOSHI , GOTOH KOHTAROH , OGAWA JUNJI
IPC: G11C7/00 , G11C11/407 , G11C7/10 , G11C7/22 , G11C8/18 , G11C11/4076 , H03K5/13 , H03L7/081
Abstract: A semiconductor integrated circuit device (20) has a command decoder (1) for issuing a control command (CNT) in accordance with a supplied control signal, a DRAM core (3), and a timing adjusting circuit (22) for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core (3). The timing adjusting circuit (22) generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock (CLKi), and generates the DRAM control signal (CNT) by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
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公开(公告)号：DE69841225D1
公开(公告)日：2009-11-19
申请号：DE69841225
申请日：1998-04-21
Applicant: FUJITSU LTD
Inventor： SAITO MIYOSHI , OGAWA JUNJI
IPC: G11C11/409 , G11C11/4091 , G06F3/00 , G11C7/06 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4096
Abstract: A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when switching the signal transmission line among the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched. This makes continuous readout possible and achieves an increase in the overall speed of the signal transmission system.
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Patent Agency Ranking
公开(公告)号：DE69837689T2
公开(公告)日：2007-08-23
申请号：DE69837689
申请日：1998-06-10
Applicant: FUJITSU LTD
Inventor： TAMURA HIROTAKA , ARAKI HISAKATSU , WAKAYAMA SHIGETOSHI , GOTOH KOHTAROH , OGAWA JUNJI
IPC: G11C7/00 , G11C11/407 , G11C7/10 , G11C7/22 , G11C8/18 , G11C11/4076 , H03K5/13 , H03L7/081
Abstract: A semiconductor integrated circuit device (20) has a command decoder (1) for issuing a control command (CNT) in accordance with a supplied control signal, a DRAM core (3), and a timing adjusting circuit (22) for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core (3). The timing adjusting circuit (22) generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock (CLKi), and generates the DRAM control signal (CNT) by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
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公开(公告)号：DE19758672B4
公开(公告)日：2004-07-15
申请号：DE19758672
申请日：1997-10-09
Applicant: FUJITSU LTD
Inventor： TAMURA HIROTAKA , SAITO MIYOSHI , GOTOH KOHTAROH , WAKAYAMA SHIGETOSHI , OGAWA JUNJI , ARAKI HISAKATSU , CHEUNG TSZ-SHING
Abstract: The system is used for signal transmission between LSI chips and has a signal transmission line with a response time equal to, or longer than, the length of a transmission symbol. The terminal resistance (51,53) for one or both ends of the transmission line is greater than the characteristic impedance of the transmission line (2). A driver output resistance is set to a higher value, or a damping resistance (7) is connected in series with the transmission line.
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公开(公告)号：DE3588121D1
公开(公告)日：1996-10-10
申请号：DE3588121
申请日：1985-05-30
Applicant: FUJITSU LTD
Inventor： NAKANO MASAO , TAKEMAE YOSHIHIRO , NAKANO TOMIO , TATEMATSU TAKEO ESUPERANSA DAI , OGAWA JUNJI , HORII TAKASHI , FUJII YASUHIRO , SATO KIMIAKI , TSUGE NORIHISA
Abstract: A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit (24) for detecting coincidence between data read from the memory unit (21) and a received input address (Ao, An). Data produced from the comparison by the comparison unit is delivered through an external connection terminal (7).
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公开(公告)号：DE3853437T2
公开(公告)日：1995-07-27
申请号：DE3853437
申请日：1988-01-18
Applicant: FUJITSU LTD
Inventor： OGAWA JUNJI
Abstract: An improved semiconductor memory device provided with an address scramble unit (50) in addition to a multidirection data selection unit (13, 18a, 18b, 19). The address scramble unit converts an external address having an addressing linearity regardless of a complex multidirection data selection into an internal address used by the multidirection data selection unit. A plurality of memory cells (10) are connected between a plurality of word lines (WL) and a plurality of bit lines (BL) to form a logical space; a plurality of boundaries being defined in a direction thereof. Each boundary includes a plurality of segments each defining a plurality of simultaneously accessible bit data. The multidirection data selection unit outputs a data in response to a segment selection signal (B1 , B0) a direction signal (SX, SY, SS) and a column address, from a boundary data selected by a row address (RA7 to RA0).
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公开(公告)号：DE3586523D1
公开(公告)日：1992-09-24
申请号：DE3586523
申请日：1985-10-14
Applicant: FUJITSU LTD
Inventor： OGAWA JUNJI
Abstract: A semiconductor memory device includes a memory cell array (1 a serial data input circuit for high-speed, large data storage in memory cells and a serial data output circuit for high-speed, large data read-out from the memory cells. The serial data input circuit includes a set (15a) of shift registers for consecutively storing serial input data (SIN) applied from an external circuit, and a set (14a) of first gates for simultaneously coupling the shift registers and a plurality of bit lines (BL) of the memory cell array to enter simultaneously the serial input data stored in the shift registers into desired memory cells selected by a desired word line. The serial data output circuit includes a set (12a) of second gates coupled to the bit lines, a set (7a) of data holding circuits, an input of each of which is connectable to the corresponding bit line through the corresponding one of the second gates, a set (11a) of third gates provided between outputs of the data holding circuits and a data bus or buses (26) and for outputting data held in the data holding circuits to the data bus or buses, and a data output circuit (9a, 10a) having a gate driving circuit for selectively driving one of the third gates. The second gates are simultaneously operated to transfer a plurality of data on a selected word line into the data holding circuit set, and the data held in the holding circuits are fed out to the data bus or buses in response to the operation of the third gates. The device can be used for high-speed, large data first-in first-out operation.
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